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3b3b00a9f8
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working on SPI
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2024-01-04 14:37:44 +00:00 |
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1a29e35097
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rewrite macros and user configurable REFERENCE
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2024-01-02 14:42:49 +00:00 |
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b0528ff456
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inertial wakeup
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2024-01-02 10:56:58 +00:00 |
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50a491a1be
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double click
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2024-01-01 13:08:06 +00:00 |
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d1ab5a8d99
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more src reg interaction
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2024-01-01 10:15:57 +00:00 |
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6352a65fec
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INT dur table
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2023-12-31 22:31:22 +00:00 |
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432bf4d421
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temperature
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2023-12-31 15:41:24 +00:00 |
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70dd2c9a1b
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ADC
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2023-12-31 15:24:40 +00:00 |
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f64bf4a72d
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all registers
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2023-12-31 14:14:12 +00:00 |
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16b40de1e1
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lis3dh_reset() and bit fiddle to prevent overwriting regs in case of user issue
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2023-12-30 20:22:29 +00:00 |
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cf48f7db54
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INT1 and INT2 config
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2023-12-30 16:23:25 +00:00 |
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87dd035d9e
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int to int_pin rename to avoid confusion with int regs
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2023-12-30 15:36:35 +00:00 |
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365bb369bb
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memset() and comments
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2023-12-29 23:42:15 +00:00 |
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9c3f912d1a
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read REFERENCE
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2023-12-29 18:19:11 +00:00 |
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84e6fa4caa
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latch interrupts + fn to clear on device
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2023-12-29 17:26:54 +00:00 |
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b0907115c2
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rename {pin1,pin2} => {int1,int2}
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2023-12-28 18:15:25 +00:00 |
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c979a449cf
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Pin config for IRQ
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2023-12-23 18:38:28 +00:00 |
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5d3d1437f9
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c99 + comments
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2023-12-23 13:31:59 +00:00 |
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11e6e65c6f
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change to float and remove unused h
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2023-12-23 10:33:28 +00:00 |
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e9472ed1f0
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pass FIFO data
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2023-12-23 10:28:43 +00:00 |
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a5b704fbfe
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filter: decently filter out DC/constant acceleration
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2023-12-22 17:00:53 +00:00 |
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9ae2d4ce01
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fix: device would sometimes corrupt its own registers.
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2023-12-22 16:25:25 +00:00 |
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0dff0b92c3
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FIFO
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2023-12-22 10:22:43 +00:00 |
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31bcd4d12f
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tidying
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2023-12-22 08:26:10 +00:00 |
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509bae290b
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working simple example
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2023-12-21 23:29:22 +00:00 |
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1726159cb8
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.
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2023-12-21 18:17:20 +00:00 |
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e25f035863
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work on C implementation
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2023-12-21 17:31:12 +00:00 |
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