all registers
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16b40de1e1
commit
f64bf4a72d
121
lis3dh.c
121
lis3dh.c
@ -37,8 +37,12 @@ int lis3dh_init(lis3dh_t *lis3dh) {
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int lis3dh_configure(lis3dh_t *lis3dh) {
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uint8_t ctrl_reg1, ctrl_reg2, ctrl_reg3;
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uint8_t ctrl_reg4, ctrl_reg5, ctrl_reg6;
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uint8_t ctrl_reg0, temp_cfg_reg;
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uint8_t fifo_ctrl_reg, int1_cfg, int2_cfg;
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uint8_t int1_ths, int2_ths, int1_dur, int2_dur;
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uint8_t click_cfg, click_ths;
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uint8_t time_limit, time_latency, time_window;
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uint8_t act_ths, act_dur;
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uint8_t ref; /* dummy */
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int err = 0;
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@ -56,44 +60,84 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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int2_ths = 0;
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int1_dur = 0;
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int2_dur = 0;
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click_cfg = 0;
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click_ths = 0;
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time_limit = 0;
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time_latency = 0;
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time_window = 0;
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act_ths = 0;
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act_dur = 0;
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ctrl_reg0 = 0;
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temp_cfg_reg = 0;
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/* determine whether to enable ADC or TEMP sensor */
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temp_cfg_reg |= (lis3dh->cfg.en_adc & 1) << 7;
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temp_cfg_reg |= (lis3dh->cfg.en_temp & 1) << 6;
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/* set time limit */
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time_limit |= (lis3dh->cfg.time_limit & 0x7F);
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/* set time latency and window */
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time_latency = lis3dh->cfg.time_latency;
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time_window = lis3dh->cfg.time_window;
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act_ths |= (lis3dh->cfg.act_ths & 0x7F);
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act_dur = lis3dh->cfg.act_dur;
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/* set click config register */
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click_cfg |= (lis3dh->cfg.click.xs & 1);
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click_cfg |= (lis3dh->cfg.click.xd & 1) << 1;
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click_cfg |= (lis3dh->cfg.click.ys & 1) << 2;
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click_cfg |= (lis3dh->cfg.click.yd & 1) << 3;
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click_cfg |= (lis3dh->cfg.click.zs & 1) << 4;
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click_cfg |= (lis3dh->cfg.click.zd & 1) << 5;
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/* CLICK threshold */
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click_ths |= (lis3dh->cfg.click_ths & 0x7F);
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click_ths |= (lis3dh->cfg.click.latch & 1) << 7;
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/* set interrupt registers */
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.click & 1) << 7;
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.ia1 & 1) << 6;
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.ia2 & 1) << 5;
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.drdy_zyxda & 1) << 4;
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.drdy_321 & 1) << 3;
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.wtm & 1) << 2;
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ctrl_reg3 |= (lis3dh->cfg.int_pin1.overrun & 1) << 1;
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ctrl_reg3 |= (lis3dh->cfg.pin1.click & 1) << 7;
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ctrl_reg3 |= (lis3dh->cfg.pin1.ia1 & 1) << 6;
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ctrl_reg3 |= (lis3dh->cfg.pin1.ia2 & 1) << 5;
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ctrl_reg3 |= (lis3dh->cfg.pin1.drdy_zyxda & 1) << 4;
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ctrl_reg3 |= (lis3dh->cfg.pin1.drdy_321 & 1) << 3;
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ctrl_reg3 |= (lis3dh->cfg.pin1.wtm & 1) << 2;
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ctrl_reg3 |= (lis3dh->cfg.pin1.overrun & 1) << 1;
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ctrl_reg6 |= (lis3dh->cfg.int_pin2.click & 1) << 7;
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ctrl_reg6 |= (lis3dh->cfg.int_pin2.ia1 & 1) << 6;
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ctrl_reg6 |= (lis3dh->cfg.int_pin2.ia2 & 1) << 5;
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ctrl_reg6 |= (lis3dh->cfg.int_pin2.boot & 1) << 4;
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ctrl_reg6 |= (lis3dh->cfg.int_pin2.act & 1) << 3;
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ctrl_reg6 |= (lis3dh->cfg.int_pin2.polarity & 1) << 1;
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ctrl_reg6 |= (lis3dh->cfg.pin2.click & 1) << 7;
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ctrl_reg6 |= (lis3dh->cfg.pin2.ia1 & 1) << 6;
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ctrl_reg6 |= (lis3dh->cfg.pin2.ia2 & 1) << 5;
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ctrl_reg6 |= (lis3dh->cfg.pin2.boot & 1) << 4;
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ctrl_reg6 |= (lis3dh->cfg.pin2.act & 1) << 3;
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ctrl_reg6 |= (lis3dh->cfg.pin2.polarity & 1) << 1;
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ctrl_reg5 |= (lis3dh->cfg.int_pin1.latch & 1) << 3;
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ctrl_reg5 |= (lis3dh->cfg.int_pin2.latch & 1) << 1;
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/* set some of CTRL_REG5 */
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ctrl_reg5 |= (lis3dh->cfg.int2.en_4d & 1);
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ctrl_reg5 |= (lis3dh->cfg.pin2.latch & 1) << 1;
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ctrl_reg5 |= (lis3dh->cfg.int1.en_4d & 1) << 2;
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ctrl_reg5 |= (lis3dh->cfg.pin1.latch & 1) << 3;
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/* set INT1_CFG and INT2_CFG */
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int1_cfg |= (lis3dh->cfg.int1_cfg.xl & 1);
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int1_cfg |= (lis3dh->cfg.int1_cfg.xh & 1) << 1;
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int1_cfg |= (lis3dh->cfg.int1_cfg.yl & 1) << 2;
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int1_cfg |= (lis3dh->cfg.int1_cfg.yh & 1) << 3;
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int1_cfg |= (lis3dh->cfg.int1_cfg.zl & 1) << 4;
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int1_cfg |= (lis3dh->cfg.int1_cfg.zh & 1) << 5;
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int1_cfg |= (lis3dh->cfg.int1_cfg.det_6d & 1) << 6;
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int1_cfg |= (lis3dh->cfg.int1_cfg.aoi & 1) << 7;
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int1_cfg |= (lis3dh->cfg.int1.xl & 1);
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int1_cfg |= (lis3dh->cfg.int1.xh & 1) << 1;
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int1_cfg |= (lis3dh->cfg.int1.yl & 1) << 2;
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int1_cfg |= (lis3dh->cfg.int1.yh & 1) << 3;
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int1_cfg |= (lis3dh->cfg.int1.zl & 1) << 4;
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int1_cfg |= (lis3dh->cfg.int1.zh & 1) << 5;
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int1_cfg |= (lis3dh->cfg.int1.en_6d & 1) << 6;
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int1_cfg |= (lis3dh->cfg.int1.aoi & 1) << 7;
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int2_cfg |= (lis3dh->cfg.int2_cfg.xl & 1);
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int2_cfg |= (lis3dh->cfg.int2_cfg.xh & 1) << 1;
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int2_cfg |= (lis3dh->cfg.int2_cfg.yl & 1) << 2;
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int2_cfg |= (lis3dh->cfg.int2_cfg.yh & 1) << 3;
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int2_cfg |= (lis3dh->cfg.int2_cfg.zl & 1) << 4;
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int2_cfg |= (lis3dh->cfg.int2_cfg.zh & 1) << 5;
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int2_cfg |= (lis3dh->cfg.int2_cfg.det_6d & 1) << 6;
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int2_cfg |= (lis3dh->cfg.int2_cfg.aoi & 1) << 7;
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int2_cfg |= (lis3dh->cfg.int2.xl & 1);
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int2_cfg |= (lis3dh->cfg.int2.xh & 1) << 1;
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int2_cfg |= (lis3dh->cfg.int2.yl & 1) << 2;
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int2_cfg |= (lis3dh->cfg.int2.yh & 1) << 3;
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int2_cfg |= (lis3dh->cfg.int2.zl & 1) << 4;
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int2_cfg |= (lis3dh->cfg.int2.zh & 1) << 5;
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int2_cfg |= (lis3dh->cfg.int2.en_6d & 1) << 6;
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int2_cfg |= (lis3dh->cfg.int2.aoi & 1) << 7;
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int1_dur = lis3dh->cfg.int1_dur & 0x7F;
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int2_dur = lis3dh->cfg.int2_dur & 0x7F;
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@ -125,7 +169,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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ctrl_reg2 |= (lis3dh->cfg.filter.ia2 & 1);
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}
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/* always set block update */
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/* always set block update (BDU) */
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ctrl_reg4 |= 0x80;
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/* set high resolution */
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@ -138,6 +182,10 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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ctrl_reg1 |= 0x08;
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}
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/* ctrl_reg0 is 0x10 | (SDO << 7) */
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ctrl_reg0 |= 0x10;
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ctrl_reg0 |= (lis3dh->cfg.sdo_pullup & 1) << 7;
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/* write these before the control regs that start the device */
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err |= lis3dh->dev.write(REG_FIFO_CTRL_REG, fifo_ctrl_reg);
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err |= lis3dh->dev.write(REG_INT1_CFG, int1_cfg);
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@ -146,7 +194,16 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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err |= lis3dh->dev.write(REG_INT2_CFG, int2_cfg);
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err |= lis3dh->dev.write(REG_INT2_THS, int2_ths);
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err |= lis3dh->dev.write(REG_INT2_DURATION, int2_dur);
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err |= lis3dh->dev.write(REG_CLICK_CFG, click_cfg);
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err |= lis3dh->dev.write(REG_CLICK_THS, click_ths);
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err |= lis3dh->dev.write(REG_TIME_LIMIT, time_limit);
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err |= lis3dh->dev.write(REG_TIME_LATENCY, time_latency);
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err |= lis3dh->dev.write(REG_TIME_WINDOW, time_window);
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err |= lis3dh->dev.write(REG_ACT_THS, act_ths);
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err |= lis3dh->dev.write(REG_ACT_DUR, act_dur);
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err |= lis3dh->dev.write(REG_TEMP_CFG_REG, temp_cfg_reg);
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err |= lis3dh->dev.write(REG_CTRL_REG0, ctrl_reg0);
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err |= lis3dh->dev.write(REG_CTRL_REG1, ctrl_reg1);
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err |= lis3dh->dev.write(REG_CTRL_REG2, ctrl_reg2);
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err |= lis3dh->dev.write(REG_CTRL_REG3, ctrl_reg3);
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41
lis3dh.h
41
lis3dh.h
@ -67,10 +67,21 @@ struct lis3dh_device {
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int (*deinit)(void);
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};
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struct lis3dh_click_config {
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uint8_t zd; /* double click interrupt on Z-axis */
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uint8_t zs; /* single click interrupt on Z-axis */
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uint8_t yd; /* double click interrupt on Y-axis */
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uint8_t ys; /* single click interrupt on Y-axis */
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uint8_t xd; /* double click interrupt on X-axis */
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uint8_t xs; /* single click interrupt on X-axis */
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uint8_t latch; /* active until CLICK_SRC is read */
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};
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/* INT1_CFG and INT2_CFG have identical struct */
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struct lis3dh_int_config {
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uint8_t aoi; /* AND/OR combination of int events */
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uint8_t det_6d; /* 6 direction detection */
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uint8_t en_6d; /* 6 direction detection */
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uint8_t en_4d; /* both en_6d and en_4d must = 1 for 4D to work ! */
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uint8_t zh; /* interrupt generation on Z high event / Dir. recog. */
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uint8_t zl; /* interrupt generation on Z low event / Dir. recog. */
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uint8_t yh; /* interrupt generation on Y high event / Dir. recog. */
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@ -87,7 +98,7 @@ struct lis3dh_int_pin2_config {
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uint8_t boot; /* enable BOOT on pin 2 */
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uint8_t act; /* interrupt on activity */
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uint8_t polarity; /* INT1 & INT2 polarity. 0 active high, 1 active low */
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uint8_t latch; /* latch interrupt until cleared */
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uint8_t latch; /* active until INT2_SRC read (reg5:1) */
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};
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/* config for INT1 trigger output */
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@ -99,7 +110,7 @@ struct lis3dh_int_pin1_config {
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uint8_t drdy_321; /* not sure */
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uint8_t wtm; /* FIFO reached watermark level */
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uint8_t overrun; /* FIFO has overrun */
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uint8_t latch; /* latch interrupt until cleared */
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uint8_t latch; /* active until INT1_SRC read (reg5:0) */
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};
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/* config for high-pass filter */
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@ -125,10 +136,11 @@ struct lis3dh_config {
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uint8_t mode; /* LPen and HR */
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struct lis3dh_fifo_config fifo;
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struct lis3dh_filter_config filter;
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struct lis3dh_int_pin1_config int_pin1;
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struct lis3dh_int_pin2_config int_pin2;
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struct lis3dh_int_config int1_cfg;
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struct lis3dh_int_config int2_cfg;
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struct lis3dh_int_pin1_config pin1;
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struct lis3dh_int_pin2_config pin2;
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struct lis3dh_int_config int1;
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struct lis3dh_int_config int2;
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struct lis3dh_click_config click;
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/* 1 LSb = 16 mg @ FS_2G
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* 1 LSb = 32 mg @ FS_4G
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@ -137,6 +149,8 @@ struct lis3dh_config {
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*/
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uint8_t int1_ths; /* 7-bit INT 1 threshold value */
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uint8_t int2_ths; /* 7-bit INT 2 threshold value */
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uint8_t click_ths; /* 7-bit CLICK threshold value */
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uint8_t act_ths; /* 7-bit ACT threshold value */
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/* Duration time is measured in N/ODR where:
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* --- N = The content of the intX_dur integer
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@ -144,6 +158,19 @@ struct lis3dh_config {
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*/
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uint8_t int1_dur; /* 7-bit INT 1 duration value */
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uint8_t int2_dur; /* 7-bit INT 2 duration value */
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/* Sleep-to-wake and return-to-sleep duration
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* 1 LSb = (8 * 1[LSb] + 1) / ODR
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*/
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uint8_t act_dur; /* 8-bit ACT duration value */
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uint8_t time_limit; /* 7-bit time limit ~ CLICK */
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uint8_t time_latency; /* 8-bit time latency ~ CLICK */
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uint8_t time_window; /* 8-bit time window ~ CLICK */
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uint8_t sdo_pullup; /* Use pull-up on SDO. default 0 use */
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uint8_t en_adc; /* enable ADC */
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uint8_t en_temp; /* enable temp sensor on ADC 3 */
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};
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/* data read not from FIFO is put here */
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4
main.c
4
main.c
@ -57,8 +57,8 @@ int main() {
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lis.cfg.rate = LIS3DH_ODR_100_HZ;
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lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM;
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lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT2;
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lis.cfg.int_pin1.wtm = 1;
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lis.cfg.int_pin1.latch = 1;
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lis.cfg.pin1.wtm = 1;
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lis.cfg.pin1.latch = 1;
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lis.cfg.filter.mode = LIS3DH_FILTER_MODE_AUTORESET;
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lis.cfg.filter.cutoff = LIS3DH_FILTER_CUTOFF_8;
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