william/lis3dh
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int to int_pin rename to avoid confusion with int regs

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This commit is contained in:
William Clark 2023-12-30 15:36:35 +00:00
parent 5bde365c65
commit 87dd035d9e
3 changed files with 23 additions and 23 deletions
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34
lis3dh.c
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@ -63,8 +63,8 @@ int lis3dh_init(lis3dh_t *lis3dh) {
lis3dh->cfg.fifo.fth = 31; /* default watermark level. */ lis3dh->cfg.fifo.fth = 31; /* default watermark level. */
memset(&lis3dh->acc, 0, sizeof lis3dh->acc); memset(&lis3dh->acc, 0, sizeof lis3dh->acc);
memset(&lis3dh->cfg.int1, 0, sizeof lis3dh->cfg.int1); memset(&lis3dh->cfg.int_pin1, 0, sizeof lis3dh->cfg.int_pin1);
memset(&lis3dh->cfg.int2, 0, sizeof lis3dh->cfg.int2); memset(&lis3dh->cfg.int_pin2, 0, sizeof lis3dh->cfg.int_pin2);
memset(&lis3dh->cfg.filter, 0, sizeof lis3dh->cfg.filter); memset(&lis3dh->cfg.filter, 0, sizeof lis3dh->cfg.filter);
lis3dh->cfg.filter.mode = 0xFF; /* in use if neq 0xFF */ lis3dh->cfg.filter.mode = 0xFF; /* in use if neq 0xFF */
@ -92,23 +92,23 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
fifo_ctrl_reg = 0; fifo_ctrl_reg = 0;
/* set interrupt registers */ /* set interrupt registers */
ctrl_reg3 |= (lis3dh->cfg.int1.click & 1) << 7; ctrl_reg3 |= (lis3dh->cfg.int_pin1.click & 1) << 7;
ctrl_reg3 |= (lis3dh->cfg.int1.ia1 & 1) << 6; ctrl_reg3 |= (lis3dh->cfg.int_pin1.ia1 & 1) << 6;
ctrl_reg3 |= (lis3dh->cfg.int1.ia2 & 1) << 5; ctrl_reg3 |= (lis3dh->cfg.int_pin1.ia2 & 1) << 5;
ctrl_reg3 |= (lis3dh->cfg.int1.drdy_zyxda & 1) << 4; ctrl_reg3 |= (lis3dh->cfg.int_pin1.drdy_zyxda & 1) << 4;
ctrl_reg3 |= (lis3dh->cfg.int1.drdy_321 & 1) << 3; ctrl_reg3 |= (lis3dh->cfg.int_pin1.drdy_321 & 1) << 3;
ctrl_reg3 |= (lis3dh->cfg.int1.wtm & 1) << 2; ctrl_reg3 |= (lis3dh->cfg.int_pin1.wtm & 1) << 2;
ctrl_reg3 |= (lis3dh->cfg.int1.overrun & 1) << 1; ctrl_reg3 |= (lis3dh->cfg.int_pin1.overrun & 1) << 1;
ctrl_reg6 |= (lis3dh->cfg.int2.click & 1) << 7; ctrl_reg6 |= (lis3dh->cfg.int_pin2.click & 1) << 7;
ctrl_reg6 |= (lis3dh->cfg.int2.ia1 & 1) << 6; ctrl_reg6 |= (lis3dh->cfg.int_pin2.ia1 & 1) << 6;
ctrl_reg6 |= (lis3dh->cfg.int2.ia2 & 1) << 5; ctrl_reg6 |= (lis3dh->cfg.int_pin2.ia2 & 1) << 5;
ctrl_reg6 |= (lis3dh->cfg.int2.boot & 1) << 4; ctrl_reg6 |= (lis3dh->cfg.int_pin2.boot & 1) << 4;
ctrl_reg6 |= (lis3dh->cfg.int2.act & 1) << 3; ctrl_reg6 |= (lis3dh->cfg.int_pin2.act & 1) << 3;
ctrl_reg6 |= (lis3dh->cfg.int2.polarity & 1) << 1; ctrl_reg6 |= (lis3dh->cfg.int_pin2.polarity & 1) << 1;
ctrl_reg5 |= (lis3dh->cfg.int1.latch & 1) << 3; ctrl_reg5 |= (lis3dh->cfg.int_pin1.latch & 1) << 3;
ctrl_reg5 |= (lis3dh->cfg.int2.latch & 1) << 1; ctrl_reg5 |= (lis3dh->cfg.int_pin2.latch & 1) << 1;
/* set enable FIFO */ /* set enable FIFO */
if (lis3dh->cfg.fifo.mode != 0xFF) { if (lis3dh->cfg.fifo.mode != 0xFF) {

8
lis3dh.h
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@ -65,7 +65,7 @@ struct lis3dh_device {
}; };
/* config for INT2 trigger output */ /* config for INT2 trigger output */
struct lis3dh_int2_config { struct lis3dh_int_pin2_config {
uint8_t click; /* CLICK interrupt */ uint8_t click; /* CLICK interrupt */
uint8_t ia1; /* IA1 interrupt */ uint8_t ia1; /* IA1 interrupt */
uint8_t ia2; /* IA2 interrupt */ uint8_t ia2; /* IA2 interrupt */
@ -76,7 +76,7 @@ struct lis3dh_int2_config {
}; };
/* config for INT1 trigger output */ /* config for INT1 trigger output */
struct lis3dh_int1_config { struct lis3dh_int_pin1_config {
uint8_t click; /* CLICK interrupt */ uint8_t click; /* CLICK interrupt */
uint8_t ia1; /* IA1 interrupt */ uint8_t ia1; /* IA1 interrupt */
uint8_t ia2; /* IA2 interrupt */ uint8_t ia2; /* IA2 interrupt */
@ -110,8 +110,8 @@ struct lis3dh_config {
uint8_t mode; /* LPen and HR */ uint8_t mode; /* LPen and HR */
struct lis3dh_fifo_config fifo; struct lis3dh_fifo_config fifo;
struct lis3dh_filter_config filter; struct lis3dh_filter_config filter;
struct lis3dh_int1_config int1; struct lis3dh_int_pin1_config int_pin1;
struct lis3dh_int2_config int2; struct lis3dh_int_pin2_config int_pin2;
}; };
/* data read not from FIFO is put here */ /* data read not from FIFO is put here */

4
main.c
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@ -52,8 +52,8 @@ int main() {
lis.cfg.rate = LIS3DH_ODR_100_HZ; lis.cfg.rate = LIS3DH_ODR_100_HZ;
lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM; lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM;
lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT2; lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT2;
lis.cfg.int1.wtm = 1; lis.cfg.int_pin1.wtm = 1;
lis.cfg.int1.latch = 1; lis.cfg.int_pin1.latch = 1;
lis.cfg.filter.mode = LIS3DH_FILTER_MODE_AUTORESET; lis.cfg.filter.mode = LIS3DH_FILTER_MODE_AUTORESET;
lis.cfg.filter.cutoff = LIS3DH_FILTER_CUTOFF_8; lis.cfg.filter.cutoff = LIS3DH_FILTER_CUTOFF_8;