Started FMMD on sigma delta

submission_thesis/CH5_Examples/Makefile

@@ -4,7 +4,7 @@ PNG_DIA = blockdiagramcircuit2.png  bubba_oscillator_block_diagram.png  circuit1
 	dubsim1.png   invamp.png   mvampcircuit.png   pd.png   plddouble.png   plddoublesymptom.png         \
 	poss1finalbubba.png   poss2finalbubba.png   pt100.png   pt100_doublef.png   pt100_singlef.png       \
 	pt100_tc.png         pt100_tc_sp.png      shared_component.png   stat_single.png    three_tree.png  \
-	tree_abstraction_levels.png   vrange.png
+	tree_abstraction_levels.png   vrange.png sigma_delta_block.png
 
 
 

submission_thesis/CH5_Examples/copy.tex

@@ -1660,6 +1660,94 @@ The following example shows the analysis of a mixed analogue and digital circuit
 
 
 
+
+\begin{figure}[h]
+ \centering
+ \includegraphics[width=200pt,keepaspectratio=true]{./CH5_Examples/sigma_delta_block.png}
+ % sigma_delta_block.png: 828x367 pixel, 72dpi, 29.21x12.95 cm, bb=0 0 828 367
+ \caption{Sigma Delta ADC signal path}
+ \label{fig:sigmadeltablock}
+\end{figure}
+
+
+\paragraph{How the circuit works.}
+The diagram in~\ref{fig:sigmadeltablock} shows the signal path used
+by this configuration for a $\Sigma \Delta $ADC.
+%
+It works by placing the analogue voltage to be read into
+a mixed analogue and digital feedback circuit.
+%
+A summing junction and integrator is used to compare the negative feedback
+signal with the input.
+%
+The output of the integrator is digitally cleaned-up by IC2 (i.e. output is TRUE or FALSE for digital logic)
+which acts as a comparator, and fed to the D type flip flop.
+%
+The output of the flip flop is a digital representation
+of the input voltage.
+%
+The output of the flip flop, is now cleaned as an analogue signal
+(i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage)
+and fed into the summing integrator completing the negative feedback loop.
+% ]
+% into
+% 
+% A summing integrator
+% adds the voltage input to the feedback signal.
+% The digital circuitry tries to 
+% apply a voltage to the integrator that will
+% produce a zero output... doh this is difficult to describe.
+% %
+% The input voltage is summed with the feedback from the circuit
+% and is fed into a comparator (IC2) that will output a plus or minus.
+% This is fed into the input (D) of a DQ flip flop.
+% This digitally buffers the output from the comparator.
+% The output from the from the DQ flkip flop is a digital representation
+% of the input voltage.
+% The output from the DQ is sent to the digital comparator formed by R3,R4
+% and IC3.
+% The output from this is sent to the summing integrator as the signal summed with the input.
+
+\subsection{Identifying initial {\fgs}}
+
+\subsubsection{Summing Junction formed by R1 and R2}
+
+The resistors R1, R2 form a summing junction
+to the negative input of IC1.
+Using the earlier definition for resistor failure modes,
+$fm(R)= \{OPEN, SHORT\}$, we analyse the summing junction
+in table~\ref{tbl:sumjunct} below.
+
+\begin{table}[h+]
+\caption{Summing Junction: Failure Mode Effects Analysis: Single Faults} % title of Table
+\label{tbl:sumjunct}
+
+\begin{tabular}{|| l | l | c | c | l ||} \hline
+ \textbf{Failure Scenario} & &  \textbf{Summing}        &   & \textbf{Symptom}          \\ 
+                           & &  \textbf{Junction}       &   &                           \\
+               \hline
+     FS1: R1  SHORT    &  &  R1 input dominates   &  &     $R1\_IN\_DOM$           \\ \hline
+     FS2: R1  OPEN     &  &  R2 input dominates   &  &     $R2\_IN\_DOM$           \\ \hline
+     FS3: R2  SHORT    &  &  R2 input dominates    &  &    $R2\_IN\_DOM$           \\ \hline
+     FS4: R2  OPEN     &  &   R1 input dominates    &  &    $R1\_IN\_DOM$           \\ \hline
+
+\hline
+
+\end{tabular}
+\end{table}  
+% PHS45 
+
+This summing junction fails with two symptoms. We create a {\dc} called $SUMJUNCT$ and we can state,
+$$fm(SUMJUNCT) = \{ R1\_IN\_DOM, R2\_IN\_DOM \} $$.
+
+
+
+%\subsection{FMMD Process applied to $\Sigma \Delta $ADC}.
+
+T%he block diagram in figure~\ref{fig
+
+
+\clearpage
 \section{PT100 Analysis: Double failures and MTTF statistics}
 {
 This section