Sigma delta CC figures written into table
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Robin Clark
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@ -1709,7 +1709,7 @@ $$ fm (DL2AL) = \{ LOW, HIGH, LOW\_{SLEW} \} $$
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% This is a single component as a {\fg}, and we can state
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% $$ fm (DCM) = \{ HIGH, LOW, NOOP \} $$
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The digital element of the {\sd}, is the one bit memory, or D type flip flop. This
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The digital element of the {\sd}, is a `one~bit~memory', or D type flip flop. This
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buffers the feedback result and provides the output bit stream.
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We create a {\fg} from the CLOCK and IC4 to model this digital buffer.
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@ -1866,7 +1866,7 @@ We now show the final {\dc} hierarchy in figure~\ref{fig:eulersdfinal}.
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The \sd example, shows that FMMD can be applied to mixed digital and analogue circuitry.
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\clearpage
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%\clearpage
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\section{Pt100 Analysis: FMMD and Double Failure Mode Analysis}
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\label{sec:Pt100}
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{
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@ -126,7 +126,7 @@ with additional indexing when appropriate.
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\paragraph{Defining a function that returns failure modes given a component.}
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The function $fm$ has a component as its domain and the components failure modes, $fms$, as its range. % (see equation~\ref{eqn:fm}).
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Where $\mathcal{F}$ is the set of all failures,
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$$ fm: \mathcal{C} \rightarrow \mathcal{F}$$.
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$$ fm: \mathcal{C} \rightarrow \mathcal{F}.$$
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We can represent the number of potential failure modes of a component $c$, to be $ | fm(c) | .$
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\paragraph{Indexing components with the group $G$.}
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@ -146,7 +146,7 @@ Where $\mathcal{G}$ represents the set of all {\fgs}, and $ \mathbb{Z}^{+} $, $C
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%
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%and, where n is the number of components in the system/{\fg},
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and $|fm(c_i)|$ is the number of failure modes
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in component ${c_i}$, is given by
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in component ${c_i}$, comparison complexity, $CC$ is given by
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\begin{equation}
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\label{eqn:CC}
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@ -369,14 +369,15 @@ $$
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%\clearpage
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\subsection{Complexity Comparison applied to previous FMMD Examples}
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All the FMMD examples in chapters \ref{sec:chap5} and \ref{sec:chap6} showed a marked reduction in comparison
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complexity compared to the RFMEA worst case figures.
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All the FMMD examples in chapters \ref{sec:chap5}
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and \ref{sec:chap6} showed a marked reduction in comparison
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complexity compared to the RFMEA worst case figures.
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To calculate RFMEA Comparison complexity equation~\ref{eqn:CC} is used.
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%
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%
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Complexity comparison vs. RFMEA for the first three examples
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are presented in table~\ref{tbl:firstcc}.
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%
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%\usepackage{multirow}
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\begin{table}
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\label{tbl:firstcc}
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@ -550,33 +551,39 @@ by more than a factor of ten.
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\multicolumn{3}{ |c| }{{\sd} FMMD Hierarchy: section~\ref{sec:sigmadelta}} \\ \hline
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%\multirow{3}{*} {Inverting Amplifier Two stage FMMD Hierarchy: section~\ref{sec:invamp}} & & \\
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\hline
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1 & & 4 & 2 \\
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1 & INVAMP & 16 & 3 \\
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0 & NIBUFF & 0 & 4 \\
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%
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% final one has 8 components 3* NIBUFF + 1 * INVAMP + 4 * PHS45
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% (8-1) * ( (3*4) + (1*16) + (4 * 4) )
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2 & {\sd} & 308 & 2 \\
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% NIBUFF PHS45
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% 8 components so LEVEL 2 (8-1) \times ( (3*4) + (4*2) + 3 ) + LEVEL 0 16 for the INVAMP
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2 & Total for {\sd}: & 328 (FMMD) & \\
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% R&C OPAMPS
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% 14 components so 13 \times ( (10*2) (4*4) )
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0 & Total for {\sd}: & 468 (RFMEA) & \\
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\hline
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1 & SUMJINT & 30 & 4 \\
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0 & HISB & 0 & 4 \\
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2 & BISJ & 8 & 2 \\ \hline
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1 & DIGBUF & 2 & 4 \\
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1 & PD & 4 & 2 \\
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2 & DL2AL & 6 & 3 \\
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3 & FFB & 5 & 2 \\ \hline
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%
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2 & {\sd} & 4 & 2 \\ \hline
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%
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%
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2 & Total for {\sd}: & 55 (FMMD) & \\
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% R&C OPAMPS
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% 14 components so (10-1) *
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0 & Total for {\sd}: & 225 (RFMEA) & \\
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\hline \hline
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\end{tabular}
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\caption{Complexity Comparison figures for the Bubba Oscillator FMMD example (see section~\ref{sec:bubba}).}
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\caption{Complexity Comparison figures for the {\sd} FMMD example (see section~\ref{sec:sigmadelta}).}
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\end{table}
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%
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The complexity figures for this mixed analogue to digital circuit are not adversely affected by the digital to
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analogue level interfacing circuitry. This is where the modular approach aids understanding and analysis.
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When following this circuit through in a traditional way, we have to follow signal paths that
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are level shifted, adding to the complication of analysing it for failures.
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% \subsection{Exponential squared to Exponential}
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%
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% can I say that ?
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%
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\section{Unitary State Component Failure Mode sets}
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\label{sec:unitarystate}
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\paragraph{Design Decision/Constraint}
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@ -204,10 +204,10 @@ $$
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FS2: $PHS45_1$ $no\_signal$ & & signal lost & & $NO_{signal}$ \\ \hline
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% FS3: $PHS45_1$ $90\_phaseshift$ & & phase shift high & & $270\_phaseshift$ \\ \hline
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FS3: $INVAMP$ $L_{up}$ & & output high & & $NO_{signal}$ \\
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FS4: $INVAMP$ $L_{dn}$ & & output low & & $NO_{signal}$ \\
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FS5: $INVAMP$ $N_{oop}$ & & output low & & $NO_{signal}$ \\
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FS6: $INVAMP$ $L_{slew}$ & & signal lost & & $NO_{signal}$ \\ \hline
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FS3: $INVAMP$ $L_{up}$ & & output high & & $NO_{signal}$ \\
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FS4: $INVAMP$ $L_{dn}$ & & output low & & $NO_{signal}$ \\
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FS5: $INVAMP$ $N_{oop}$ & & output low & & $NO_{signal}$ \\
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FS6: $INVAMP$ $L_{slew}$ & & signal lost & & $NO_{signal}$ \\ \hline
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\hline
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