Pin config for IRQ
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eac1eaa041
commit
c979a449cf
62
lis3dh.c
62
lis3dh.c
@ -51,42 +51,84 @@ int lis3dh_init(lis3dh_t *lis3dh) {
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lis3dh->acc.x = 0.0;
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lis3dh->acc.y = 0.0;
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lis3dh->acc.z = 0.0;
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lis3dh->cfg.rate = 0;
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lis3dh->cfg.range = 0;
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lis3dh->cfg.mode = 0;
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lis3dh->cfg.fifo.mode = 0xFF; /* in use if neq 0xFF */
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lis3dh->cfg.fifo.trig = 0;
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lis3dh->cfg.fifo.fth = 32; /* default watermark level. */
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lis3dh->cfg.filter.mode = 0xFF; /* in use if neq 0xFF */
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lis3dh->cfg.filter.cutoff = 0;
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lis3dh->cfg.filter.fds = 1; /* bypass OFF by default */
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lis3dh->cfg.filter.hpclick = 0;
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lis3dh->cfg.filter.click = 0;
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lis3dh->cfg.filter.ia1 = 0;
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lis3dh->cfg.filter.ia2 = 0;
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lis3dh->cfg.pin1.click = 0;
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lis3dh->cfg.pin1.ia1 = 0;
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lis3dh->cfg.pin1.ia2 = 0;
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lis3dh->cfg.pin1.drdy_zyxda = 0;
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lis3dh->cfg.pin1.drdy_321 = 0;
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lis3dh->cfg.pin1.wtm = 0;
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lis3dh->cfg.pin1.overrun = 0;
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lis3dh->cfg.pin2.click = 0;
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lis3dh->cfg.pin2.ia1 = 0;
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lis3dh->cfg.pin2.ia2 = 0;
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lis3dh->cfg.pin2.boot = 0;
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lis3dh->cfg.pin2.act = 0;
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lis3dh->cfg.pin2.polarity = 0;
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err |= lis3dh_reset(lis3dh);
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return err;
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}
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int lis3dh_configure(lis3dh_t *lis3dh) {
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uint8_t ctrl_reg1, ctrl_reg2, ctrl_reg4, ctrl_reg5;
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uint8_t ctrl_reg1, ctrl_reg2, ctrl_reg3;
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uint8_t ctrl_reg4, ctrl_reg5, ctrl_reg6;
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uint8_t fifo_ctrl_reg;
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uint8_t ref;
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uint8_t ref; /* dummy */
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int err = 0;
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/* last 0b111 enables Z, Y and X axis */
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/* the 0x07 enables Z, Y and X axis in that order */
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ctrl_reg1 = 0 | (lis3dh->cfg.rate << 4) | 0x07;
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ctrl_reg2 = 0;
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ctrl_reg3 = 0;
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ctrl_reg4 = 0 | (lis3dh->cfg.range << 4);
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ctrl_reg5 = 0;
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ctrl_reg6 = 0;
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fifo_ctrl_reg = 0;
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/* set pin interrupt settings */
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ctrl_reg3 |= (lis3dh->cfg.pin1.click & 1) << 7;
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ctrl_reg3 |= (lis3dh->cfg.pin1.ia1 & 1) << 6;
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ctrl_reg3 |= (lis3dh->cfg.pin1.ia2 & 1) << 5;
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ctrl_reg3 |= (lis3dh->cfg.pin1.drdy_zyxda & 1) << 4;
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ctrl_reg3 |= (lis3dh->cfg.pin1.drdy_321 & 1) << 3;
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ctrl_reg3 |= (lis3dh->cfg.pin1.wtm & 1) << 2;
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ctrl_reg3 |= (lis3dh->cfg.pin1.overrun & 1) << 1;
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ctrl_reg6 |= (lis3dh->cfg.pin2.click & 1) << 7;
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ctrl_reg6 |= (lis3dh->cfg.pin2.ia1 & 1) << 6;
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ctrl_reg6 |= (lis3dh->cfg.pin2.ia2 & 1) << 5;
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ctrl_reg6 |= (lis3dh->cfg.pin2.boot & 1) << 4;
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ctrl_reg6 |= (lis3dh->cfg.pin2.act & 1) << 3;
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ctrl_reg6 |= (lis3dh->cfg.pin2.polarity & 1) << 1;
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/* set enable FIFO */
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if (lis3dh->cfg.fifo.mode != 0xFF) {
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ctrl_reg5 |= 0x40;
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fifo_ctrl_reg |= (lis3dh->cfg.fifo.fth & 0x1F);
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ctrl_reg5 |= 0x40; /* bit FIFO_EN */
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/* restrict maximum fifo size */
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if (lis3dh->cfg.fifo.fth > 32) {
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lis3dh->cfg.fifo.fth = 32;
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}
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fifo_ctrl_reg |= (lis3dh->cfg.fifo.fth);
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fifo_ctrl_reg |= (lis3dh->cfg.fifo.mode << 6);
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fifo_ctrl_reg |= ((lis3dh->cfg.fifo.trig & 1) << 5);
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}
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@ -96,7 +138,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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ctrl_reg2 |= ((lis3dh->cfg.filter.mode & 0x03) << 6);
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ctrl_reg2 |= ((lis3dh->cfg.filter.cutoff & 0x03) << 4);
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ctrl_reg2 |= ((lis3dh->cfg.filter.fds & 1) << 3);
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ctrl_reg2 |= ((lis3dh->cfg.filter.hpclick & 1) << 2);
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ctrl_reg2 |= ((lis3dh->cfg.filter.click & 1) << 2);
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ctrl_reg2 |= ((lis3dh->cfg.filter.ia1 & 1) << 1);
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ctrl_reg2 |= (lis3dh->cfg.filter.ia2 & 1);
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}
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@ -116,8 +158,10 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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err |= lis3dh->dev.write(REG_CTRL_REG1, ctrl_reg1);
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err |= lis3dh->dev.write(REG_CTRL_REG2, ctrl_reg2);
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err |= lis3dh->dev.write(REG_CTRL_REG3, ctrl_reg3);
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err |= lis3dh->dev.write(REG_CTRL_REG4, ctrl_reg4);
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err |= lis3dh->dev.write(REG_CTRL_REG5, ctrl_reg5);
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err |= lis3dh->dev.write(REG_CTRL_REG6, ctrl_reg6);
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err |= lis3dh->dev.write(REG_FIFO_CTRL_REG, fifo_ctrl_reg);
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/* read REFERENCE to clear internal filter struct */
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@ -129,7 +173,6 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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}
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int lis3dh_poll(lis3dh_t *lis3dh) {
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uint8_t status;
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int err = 0;
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@ -172,7 +215,6 @@ static uint8_t acc_shift(lis3dh_t *lis3dh) {
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/* returns a scalar that when multiplied with axis reading
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turns it to a multiple of mg. */
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static uint8_t acc_sensitivity(lis3dh_t *lis3dh) {
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uint8_t mode = lis3dh->cfg.mode;
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switch (lis3dh->cfg.range) {
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37
lis3dh.h
37
lis3dh.h
@ -63,19 +63,38 @@ struct lis3dh_device {
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int (*deinit)(void);
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};
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struct lis3dh_pin2_config {
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uint8_t click; /* CLICK interrupt */
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uint8_t ia1; /* IA1 interrupt */
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uint8_t ia2; /* IA2 interrupt */
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uint8_t boot; /* enable BOOT on pin 2 */
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uint8_t act; /* interrupt on activity */
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uint8_t polarity; /* INT1 & INT2 polarity. 0 active high, 1 active low */
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};
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struct lis3dh_pin1_config {
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uint8_t click; /* CLICK interrupt */
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uint8_t ia1; /* IA1 interrupt */
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uint8_t ia2; /* IA2 interrupt */
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uint8_t drdy_zyxda; /* new [xyz] data ready (not via FIFO) */
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uint8_t drdy_321; /* not sure */
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uint8_t wtm; /* FIFO reached watermark level */
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uint8_t overrun; /* FIFO has overrun */
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};
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struct lis3dh_filter_config {
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uint8_t mode;
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uint8_t cutoff;
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uint8_t fds; /* 1 -> use this filter */
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uint8_t hpclick; /* 1 -> use for "CLICK" function */
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uint8_t ia2; /* 1 -> use for AOI func on INT 2 */
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uint8_t ia1; /* 1 -> use for AOI func on INT 1 */
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uint8_t mode; /* filter mode, reset behaviour */
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uint8_t cutoff; /* high-pass filter cutoff freq (~ ODR) */
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uint8_t fds; /* ¬(bypass filter) */
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uint8_t click; /* enable filter for CLICK function */
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uint8_t ia2; /* enable filter for AOI func on INT 2 */
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uint8_t ia1; /* enable filter for AOI func on INT 1 */
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};
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struct lis3dh_fifo_config {
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uint8_t fth; /* user-specified watermark level 0-32 */
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uint8_t trig;
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uint8_t mode;
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uint8_t trig; /* pin to trigger when watermark/overrun occurs */
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uint8_t mode; /* FIFO mode */
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};
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struct lis3dh_config {
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@ -84,6 +103,8 @@ struct lis3dh_config {
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uint8_t mode; /* LPen and HR */
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struct lis3dh_fifo_config fifo;
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struct lis3dh_filter_config filter;
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struct lis3dh_pin1_config pin1;
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struct lis3dh_pin2_config pin2;
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};
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struct lis3dh_acceleration {
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