william/lis3dh
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fix: device would sometimes corrupt its own registers.

Browse Source
This commit is contained in:
William Clark 2023-12-22 16:25:25 +00:00
parent 0dff0b92c3
commit 9ae2d4ce01
4 changed files with 31 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored Normal file
View File

@ -0,0 +1 @@
lis3dh

37
lis3dh.c
View File

@ -2,11 +2,35 @@
#include "lis3dh.h" #include "lis3dh.h"
#include "registers.h" #include "registers.h"
static int lis3dh_reboot(lis3dh_t *lis3dh) { /* reset user regs and reload trim params */
static int lis3dh_reset(lis3dh_t *lis3dh) {
int err = 0; int err = 0;
/* set BOOT bit so device reloads internal trim parameters */
err |= lis3dh->dev.write(REG_CTRL_REG5, 0x80); err |= lis3dh->dev.write(REG_CTRL_REG5, 0x80);
lis3dh->dev.sleep(5000); /* sleep 5 ms */
/* write default values to rw regs */
err |= lis3dh->dev.write(REG_CTRL_REG0, 0b10000);
err |= lis3dh->dev.write(REG_CTRL_REG1, 0b111);
err |= lis3dh->dev.write(REG_CTRL_REG2, 0);
err |= lis3dh->dev.write(REG_CTRL_REG3, 0);
err |= lis3dh->dev.write(REG_CTRL_REG4, 0);
err |= lis3dh->dev.write(REG_CTRL_REG5, 0);
err |= lis3dh->dev.write(REG_CTRL_REG6, 0);
err |= lis3dh->dev.write(REG_FIFO_CTRL_REG, 0);
err |= lis3dh->dev.write(REG_INT1_CFG, 0);
err |= lis3dh->dev.write(REG_INT1_THS, 0);
err |= lis3dh->dev.write(REG_INT1_DURATION, 0);
err |= lis3dh->dev.write(REG_INT2_CFG, 0);
err |= lis3dh->dev.write(REG_INT2_THS, 0);
err |= lis3dh->dev.write(REG_INT2_DURATION, 0);
err |= lis3dh->dev.write(REG_CLICK_CFG, 0);
err |= lis3dh->dev.write(REG_CLICK_THS, 0);
err |= lis3dh->dev.write(REG_TIME_LIMIT, 0);
err |= lis3dh->dev.write(REG_TIME_LATENCY, 0);
err |= lis3dh->dev.write(REG_TIME_WINDOW, 0);
err |= lis3dh->dev.write(REG_ACT_THS, 0);
err |= lis3dh->dev.write(REG_ACT_DUR, 0);
return err; return err;
} }
@ -31,12 +55,11 @@ int lis3dh_init(lis3dh_t *lis3dh) {
lis3dh->cfg.rate = 0; lis3dh->cfg.rate = 0;
lis3dh->cfg.range = 0; lis3dh->cfg.range = 0;
lis3dh->cfg.mode = 0; lis3dh->cfg.mode = 0;
lis3dh->cfg.fifo.mode = 0; lis3dh->cfg.fifo.mode = 0xFF; /* in use if neq 0xFF */
lis3dh->cfg.fifo.trig = 0; lis3dh->cfg.fifo.trig = 0;
lis3dh->cfg.fifo.fth = 0; lis3dh->cfg.fifo.fth = 0;
lis3dh->cfg.fifo.enable = 0;
err |= lis3dh_reboot(lis3dh); err |= lis3dh_reset(lis3dh);
return err; return err;
} }
@ -55,7 +78,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
fifo_ctrl_reg = 0; fifo_ctrl_reg = 0;
/* set enable FIFO */ /* set enable FIFO */
if (lis3dh->cfg.fifo.enable) { if (lis3dh->cfg.fifo.mode != 0xFF) {
ctrl_reg5 |= 0x40; ctrl_reg5 |= 0x40;
fifo_ctrl_reg |= (lis3dh->cfg.fifo.fth & 0x1F); fifo_ctrl_reg |= (lis3dh->cfg.fifo.fth & 0x1F);
fifo_ctrl_reg |= (lis3dh->cfg.fifo.mode << 6); fifo_ctrl_reg |= (lis3dh->cfg.fifo.mode << 6);
@ -84,7 +107,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
err |= lis3dh->dev.read(REG_REFERENCE, &ref, 1); err |= lis3dh->dev.read(REG_REFERENCE, &ref, 1);
/* sleep for a period TBD ~ ODR */ /* sleep for a period TBD ~ ODR */
lis3dh->dev.sleep(5000); /* 5 ms */ lis3dh->dev.sleep(50000); /* 50 ms */
return err; return err;
} }

1
lis3dh.h
View File

@ -49,7 +49,6 @@ struct lis3dh_fifo_config {
uint8_t fth; uint8_t fth;
uint8_t trig; uint8_t trig;
uint8_t mode; uint8_t mode;
uint8_t enable;
}; };
struct lis3dh_config { struct lis3dh_config {

1
main.c
View File

@ -31,7 +31,6 @@ int main() {
lis.cfg.mode = LIS3DH_MODE_NORMAL; lis.cfg.mode = LIS3DH_MODE_NORMAL;
lis.cfg.range = LIS3DH_FS_2G; lis.cfg.range = LIS3DH_FS_2G;
lis.cfg.rate = LIS3DH_ODR_100_HZ; lis.cfg.rate = LIS3DH_ODR_100_HZ;
lis.cfg.fifo.enable = 1;
lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_NORMAL; lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_NORMAL;
if (lis3dh_configure(&lis)) { if (lis3dh_configure(&lis)) {