c99 + comments
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11e6e65c6f
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2
Makefile
2
Makefile
@ -1,5 +1,5 @@
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CC=gcc
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CFLAGS=-O2 -std=gnu99 -W -Werror -Wall -Wextra -I.
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CFLAGS=-O2 -std=c99 -W -Werror -Wall -Wextra -pedantic -I.
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LFLAGS=-lm
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all:
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$(CC) $(CFLAGS) main.c i2c.c lis3dh.c -o lis3dh $(LFLAGS)
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50
lis3dh.c
50
lis3dh.c
@ -9,27 +9,27 @@ static int lis3dh_reset(lis3dh_t *lis3dh) {
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err |= lis3dh->dev.write(REG_CTRL_REG5, 0x80);
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/* write default values to rw regs */
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err |= lis3dh->dev.write(REG_CTRL_REG0, 0b10000);
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err |= lis3dh->dev.write(REG_CTRL_REG1, 0b111);
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err |= lis3dh->dev.write(REG_CTRL_REG2, 0);
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err |= lis3dh->dev.write(REG_CTRL_REG3, 0);
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err |= lis3dh->dev.write(REG_CTRL_REG4, 0);
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err |= lis3dh->dev.write(REG_CTRL_REG5, 0);
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err |= lis3dh->dev.write(REG_CTRL_REG6, 0);
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err |= lis3dh->dev.write(REG_FIFO_CTRL_REG, 0);
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err |= lis3dh->dev.write(REG_INT1_CFG, 0);
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err |= lis3dh->dev.write(REG_INT1_THS, 0);
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err |= lis3dh->dev.write(REG_INT1_DURATION, 0);
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err |= lis3dh->dev.write(REG_INT2_CFG, 0);
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err |= lis3dh->dev.write(REG_INT2_THS, 0);
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err |= lis3dh->dev.write(REG_INT2_DURATION, 0);
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err |= lis3dh->dev.write(REG_CLICK_CFG, 0);
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err |= lis3dh->dev.write(REG_CLICK_THS, 0);
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err |= lis3dh->dev.write(REG_TIME_LIMIT, 0);
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err |= lis3dh->dev.write(REG_TIME_LATENCY, 0);
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err |= lis3dh->dev.write(REG_TIME_WINDOW, 0);
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err |= lis3dh->dev.write(REG_ACT_THS, 0);
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err |= lis3dh->dev.write(REG_ACT_DUR, 0);
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err |= lis3dh->dev.write(REG_CTRL_REG0, 0x10);
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err |= lis3dh->dev.write(REG_CTRL_REG1, 0x07);
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err |= lis3dh->dev.write(REG_CTRL_REG2, 0x00);
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err |= lis3dh->dev.write(REG_CTRL_REG3, 0x00);
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err |= lis3dh->dev.write(REG_CTRL_REG4, 0x00);
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err |= lis3dh->dev.write(REG_CTRL_REG5, 0x00);
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err |= lis3dh->dev.write(REG_CTRL_REG6, 0x00);
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err |= lis3dh->dev.write(REG_FIFO_CTRL_REG, 0x00);
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err |= lis3dh->dev.write(REG_INT1_CFG, 0x00);
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err |= lis3dh->dev.write(REG_INT1_THS, 0x00);
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err |= lis3dh->dev.write(REG_INT1_DURATION, 0x00);
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err |= lis3dh->dev.write(REG_INT2_CFG, 0x00);
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err |= lis3dh->dev.write(REG_INT2_THS, 0x00);
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err |= lis3dh->dev.write(REG_INT2_DURATION, 0x00);
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err |= lis3dh->dev.write(REG_CLICK_CFG, 0x00);
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err |= lis3dh->dev.write(REG_CLICK_THS, 0x00);
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err |= lis3dh->dev.write(REG_TIME_LIMIT, 0x00);
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err |= lis3dh->dev.write(REG_TIME_LATENCY, 0x00);
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err |= lis3dh->dev.write(REG_TIME_WINDOW, 0x00);
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err |= lis3dh->dev.write(REG_ACT_THS, 0x00);
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err |= lis3dh->dev.write(REG_ACT_DUR, 0x00);
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return err;
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}
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@ -77,7 +77,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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int err = 0;
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/* last 0b111 enables Z, Y and X axis */
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ctrl_reg1 = 0 | (lis3dh->cfg.rate << 4) | 0b111;
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ctrl_reg1 = 0 | (lis3dh->cfg.rate << 4) | 0x07;
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ctrl_reg2 = 0;
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ctrl_reg4 = 0 | (lis3dh->cfg.range << 4);
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ctrl_reg5 = 0;
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@ -93,8 +93,8 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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/* set enable filter */
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if (lis3dh->cfg.filter.mode != 0xFF) {
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ctrl_reg2 |= ((lis3dh->cfg.filter.mode & 0b11) << 6);
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ctrl_reg2 |= ((lis3dh->cfg.filter.cutoff & 0b11) << 4);
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ctrl_reg2 |= ((lis3dh->cfg.filter.mode & 0x03) << 6);
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ctrl_reg2 |= ((lis3dh->cfg.filter.cutoff & 0x03) << 4);
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ctrl_reg2 |= ((lis3dh->cfg.filter.fds & 1) << 3);
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ctrl_reg2 |= ((lis3dh->cfg.filter.hpclick & 1) << 2);
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ctrl_reg2 |= ((lis3dh->cfg.filter.ia1 & 1) << 1);
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@ -111,7 +111,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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/* set LPen */
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if (lis3dh->cfg.mode == LIS3DH_MODE_LP) {
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ctrl_reg1 |= 0b1000;
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ctrl_reg1 |= 0x08;
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}
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err |= lis3dh->dev.write(REG_CTRL_REG1, ctrl_reg1);
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68
lis3dh.h
68
lis3dh.h
@ -4,55 +4,55 @@
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#include <stdint.h>
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/* rates */
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#define LIS3DH_ODR_POWEROFF 0b0000
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#define LIS3DH_ODR_1_HZ 0b0001
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#define LIS3DH_ODR_10_HZ 0b0010
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#define LIS3DH_ODR_25_HZ 0b0011
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#define LIS3DH_ODR_50_HZ 0b0100
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#define LIS3DH_ODR_100_HZ 0b0101
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#define LIS3DH_ODR_200_HZ 0b0110
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#define LIS3DH_ODR_400_HZ 0b0111
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#define LIS3DH_ODR_NORM_1344_HZ 0b1001
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#define LIS3DH_ODR_LP_1600_HZ 0b1000
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#define LIS3DH_ODR_LP_5376_HZ 0b1001
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#define LIS3DH_ODR_POWEROFF 0x00
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#define LIS3DH_ODR_1_HZ 0x01
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#define LIS3DH_ODR_10_HZ 0x02
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#define LIS3DH_ODR_25_HZ 0x03
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#define LIS3DH_ODR_50_HZ 0x04
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#define LIS3DH_ODR_100_HZ 0x05
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#define LIS3DH_ODR_200_HZ 0x06
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#define LIS3DH_ODR_400_HZ 0x07
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#define LIS3DH_ODR_NORM_1344_HZ 0x09
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#define LIS3DH_ODR_LP_1600_HZ 0x08
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#define LIS3DH_ODR_LP_5376_HZ 0x09
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/* range/sens */
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#define LIS3DH_FS_2G 0b00
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#define LIS3DH_FS_4G 0b01
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#define LIS3DH_FS_8G 0b10
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#define LIS3DH_FS_16G 0b11
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#define LIS3DH_FS_2G 0x00
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#define LIS3DH_FS_4G 0x01
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#define LIS3DH_FS_8G 0x02
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#define LIS3DH_FS_16G 0x03
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/* operating modes */
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#define LIS3DH_MODE_HR 0b00
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#define LIS3DH_MODE_LP 0b01
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#define LIS3DH_MODE_NORMAL 0b10
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#define LIS3DH_MODE_HR 0x00
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#define LIS3DH_MODE_LP 0x01
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#define LIS3DH_MODE_NORMAL 0x02
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/* FIFO modes */
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#define LIS3DH_FIFO_MODE_BYPASS 0b00
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#define LIS3DH_FIFO_MODE_NORMAL 0b01 /* "FIFO" */
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#define LIS3DH_FIFO_MODE_STREAM 0b10
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#define LIS3DH_FIFO_MODE_STREAM_TO_FIFO 0b11
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#define LIS3DH_FIFO_MODE_BYPASS 0x00
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#define LIS3DH_FIFO_MODE_NORMAL 0x01 /* "FIFO" */
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#define LIS3DH_FIFO_MODE_STREAM 0x02
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#define LIS3DH_FIFO_MODE_STREAM_TO_FIFO 0x03
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/* FIFO trigger pin selection */
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#define LIS3DH_FIFO_TRIG_INT1 0b0
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#define LIS3DH_FIFO_TRIG_INT2 0b1
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#define LIS3DH_FIFO_TRIG_INT1 0x00
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#define LIS3DH_FIFO_TRIG_INT2 0x01
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/* filter modes */
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/* this one is reset by reading REFERENCE (0x26) */
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#define LIS3DH_FILTER_MODE_NORMAL 0b00
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#define LIS3DH_FILTER_MODE_REFERENCE 0b01
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#define LIS3DH_FILTER_MODE_NORMAL2 0b10 /* same as 00? */
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#define LIS3DH_FILTER_MODE_AUTORESET 0b11
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#define LIS3DH_FILTER_MODE_NORMAL 0x00
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#define LIS3DH_FILTER_MODE_REFERENCE 0x01
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#define LIS3DH_FILTER_MODE_NORMAL2 0x02 /* same as 00? */
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#define LIS3DH_FILTER_MODE_AUTORESET 0x03
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/* filter cutoff */
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/* unfortunately, there is only a table for low-power mode,
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and the actual cutoff-frequency depends on the ODR.
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Naming scheme after ODR@400Hz
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AN3308 > section 4.3.1.1 */
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#define LIS3DH_FILTER_CUTOFF_8 0b00 /* highest freq */
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#define LIS3DH_FILTER_CUTOFF_4 0b01
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#define LIS3DH_FILTER_CUTOFF_2 0b10
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#define LIS3DH_FILTER_CUTOFF_1 0b11 /* lowest freq */
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#define LIS3DH_FILTER_CUTOFF_8 0x00 /* highest freq */
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#define LIS3DH_FILTER_CUTOFF_4 0x01
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#define LIS3DH_FILTER_CUTOFF_2 0x02
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#define LIS3DH_FILTER_CUTOFF_1 0x03 /* lowest freq */
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struct lis3dh_device {
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@ -73,9 +73,9 @@ struct lis3dh_filter_config {
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};
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struct lis3dh_fifo_config {
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uint8_t fth;
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uint8_t fth; /* user-specified watermark level 0-32 */
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uint8_t trig;
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uint8_t mode;
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uint8_t mode;
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};
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struct lis3dh_config {
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33
main.c
33
main.c
@ -1,19 +1,29 @@
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#define _GNU_SOURCE
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <math.h>
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#include "lis3dh.h"
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#include "i2c.h"
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/* calc magnitude of accel [x y z] vector */
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float mag(float x, float y, float z) {
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return sqrt( powf(x, 2) + powf(y, 2) + powf(z, 2) );
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}
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/* print message then exit */
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void quit(const char *msg, lis3dh_t *lis) {
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lis->dev.deinit();
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fprintf(stderr, "%s\n", msg);
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exit(1);
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}
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int main() {
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lis3dh_t lis;
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struct lis3dh_fifo_data fifo;
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/* set fn ptrs to rw on bus (i2c or SPI) */
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lis.dev.init = i2c_init;
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lis.dev.read = i2c_read;
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lis.dev.write = i2c_write;
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@ -21,28 +31,32 @@ int main() {
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lis.dev.deinit = i2c_deinit;
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/* write config after init() */
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/* initialise struct */
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if (lis3dh_init(&lis)) {
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puts("init ERR");
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quit("init()", &lis);
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}
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/* set up config */
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lis.cfg.mode = LIS3DH_MODE_HR;
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lis.cfg.range = LIS3DH_FS_2G;
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lis.cfg.rate = LIS3DH_ODR_100_HZ;
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lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM;
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/* write device config */
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if (lis3dh_configure(&lis)) {
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puts("configure ERR");
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quit("configure()", &lis);
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}
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for(int i=0; i<100; i++) {
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for (int i=0; i<50; i++) {
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/* poll fifo reg */
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if (lis3dh_poll_fifo(&lis)) {
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puts("poll_fifo ERR");
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quit("poll_fifo()", &lis);
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}
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/* read stored fifo data into `fifo' struct */
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if (lis3dh_read_fifo(&lis, &fifo)) {
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puts("read_fifo ERR");
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quit("read_fifo()", &lis);
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}
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for(int k=0; k<fifo.size; k++) {
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@ -50,10 +64,11 @@ int main() {
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fifo.x[k], fifo.y[k], fifo.z[k],
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mag(fifo.x[k], fifo.y[k], fifo.z[k]));
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}
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}
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}
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/* deinitalise struct */
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if (lis3dh_deinit(&lis)) {
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puts("deinit ERR");
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quit("deinit()", &lis);
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}
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return 0;
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