diff --git a/example/README.md b/example/README.md index 5d47c47..aa287a2 100644 --- a/example/README.md +++ b/example/README.md @@ -12,11 +12,13 @@ The watermark level can be adjusted to a value [1-32] (0 disables FIFO) by modif The FIFO "engine" samples/appends another set of [x y z] values at 1/ODR. The maximum ODR supported by the FIFO "engine" is 200 Hz. +**files in `fifo/` dir** + | FIFO mode | symbol | description | |------------------|-----------------------|----------------------------| | Bypass | `LIS3DH_FIFO_MODE_BYPASS` | FIFO is inoperational | -| FIFO | `LIS3DH_FIFO_MODE_FIFO` | FIFO can be read/emptied at any time but once overrun has to be reset. See file: `fifo-mode-fifo.c` | -| Stream | `LIS3DH_FIFO_MODE_STREAM` | FIFO continously writes new data at 1/ODR and will overwrite old data until it is read/emptied. See file: `fifo-mode-stream.c` | +| FIFO | `LIS3DH_FIFO_MODE_FIFO` | FIFO can be read/emptied at any time but once overrun has to be reset. See files: `fifo-int-ovrn.c`, `fifo-int-wtm.c`, `fifo.c` | +| Stream | `LIS3DH_FIFO_MODE_STREAM` | FIFO continously writes new data at 1/ODR and will overwrite old data until it is read/emptied. See files: `stream-int-ovrn.c`, `stream-int-wtm.c`, `stream.c` | | Stream_to_FIFO | `LIS3DH_FIFO_STREAM_TO_FIFO` | FIFO behaves like Stream mode until a set interrupt is activated, then changes to a mode FIFO. | Note: FIFO will not trigger a watermark interrupt (`pin1.wtm`) if the FIFO size is default (32; maximum size). To use the watermark interrupt, the FIFO size has to be between [1-31]. An overrun interrupt (`pin1.overrun`) will always trigger when the FIFO is full, regardless of programmed capacity. diff --git a/example/fifo-mode-fifo.c b/example/fifo-mode-fifo.c deleted file mode 100644 index 038fc80..0000000 --- a/example/fifo-mode-fifo.c +++ /dev/null @@ -1,49 +0,0 @@ -#define _GNU_SOURCE -#include -#include -#include "lis3dh.h" -#include "i2c.h" -#include "interrupt.h" - -#define GPIO_INTERRUPT_PIN_INT1 12 - -int main() { - - lis3dh_t lis; - struct lis3dh_fifo_data fifo; - int i; - - lis.dev.init = i2c_init; - lis.dev.read = i2c_read; - lis.dev.write = i2c_write; - lis.dev.sleep = usleep; - lis.dev.deinit = i2c_deinit; - - lis3dh_init(&lis); - lis3dh_reset(&lis); - int_register(GPIO_INTERRUPT_PIN_INT1); - - lis.cfg.mode = LIS3DH_MODE_HR; - lis.cfg.range = LIS3DH_FS_2G; - lis.cfg.rate = LIS3DH_ODR_100_HZ; - lis.cfg.pin1.overrun = 1; - lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_FIFO; - lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; - - lis3dh_configure(&lis); - - for ( ;; ) { - - int_poll(GPIO_INTERRUPT_PIN_INT1); - lis3dh_read_fifo(&lis, &fifo); - for(i=0; i -#include -#include "lis3dh.h" -#include "i2c.h" -#include "interrupt.h" - -#define GPIO_INTERRUPT_PIN_INT1 12 - -int main() { - - lis3dh_t lis; - struct lis3dh_fifo_data fifo; - int i; - - lis.dev.init = i2c_init; - lis.dev.read = i2c_read; - lis.dev.write = i2c_write; - lis.dev.sleep = usleep; - lis.dev.deinit = i2c_deinit; - - lis3dh_init(&lis); - lis3dh_reset(&lis); - int_register(GPIO_INTERRUPT_PIN_INT1); - - lis.cfg.mode = LIS3DH_MODE_HR; - lis.cfg.range = LIS3DH_FS_2G; - lis.cfg.rate = LIS3DH_ODR_100_HZ; - lis.cfg.pin1.overrun = 1; - lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM; - lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; - - lis3dh_configure(&lis); - - for ( ;; ) { - - int_poll(GPIO_INTERRUPT_PIN_INT1); - lis3dh_read_fifo(&lis, &fifo); - for(i=0; i /* usleep() */ +#include +#include "lis3dh.h" +#include "i2c.h" +#include "interrupt.h" + +/* Raspberry Pi GPIO pin connected to LIS3DH INT1 pin */ +#define GPIO_INTERRUPT_PIN_INT1 12 + +int main() { + + lis3dh_t lis; + struct lis3dh_fifo_data fifo; + int i; + + lis.dev.init = i2c_init; + lis.dev.read = i2c_read; + lis.dev.write = i2c_write; + lis.dev.sleep = usleep; + lis.dev.deinit = i2c_deinit; + + /* initialise struct and check device id */ + if (lis3dh_init(&lis)) { + /* error handling */ + } + + /* reset just in case*/ + if (lis3dh_reset(&lis)) { + /* error handling */ + } + + /* register interrupt */ + if (int_register(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + lis.cfg.mode = LIS3DH_MODE_HR; + lis.cfg.range = LIS3DH_FS_2G; + lis.cfg.rate = LIS3DH_ODR_100_HZ; + lis.cfg.pin1.overrun = 1; + lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_FIFO; + lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; + + /* write cfg to device */ + if (lis3dh_configure(&lis)) { + /* error handling */ + } + + for ( ;; ) { + + /* wait until FIFO overrun interrupt is active */ + if (int_poll(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + /* read FIFO into `fifo_data' struct `fifo' */ + if (lis3dh_read_fifo(&lis, &fifo)) { + /* error handling */ + } + + /* print data .. */ + for(i=0; i /* usleep() */ +#include +#include "lis3dh.h" +#include "i2c.h" +#include "interrupt.h" + +/* Raspberry Pi GPIO pin connected to LIS3DH INT1 pin */ +#define GPIO_INTERRUPT_PIN_INT1 12 + +int main() { + + lis3dh_t lis; + struct lis3dh_fifo_data fifo; + int i; + + lis.dev.init = i2c_init; + lis.dev.read = i2c_read; + lis.dev.write = i2c_write; + lis.dev.sleep = usleep; + lis.dev.deinit = i2c_deinit; + + /* initialise struct and check device id */ + if (lis3dh_init(&lis)) { + /* error handling */ + } + + /* reset just in case*/ + if (lis3dh_reset(&lis)) { + /* error handling */ + } + + /* register interrupt */ + if (int_register(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + lis.cfg.mode = LIS3DH_MODE_HR; + lis.cfg.range = LIS3DH_FS_2G; + lis.cfg.rate = LIS3DH_ODR_100_HZ; + lis.cfg.pin1.wtm = 1; /* watermark interrupt */ + lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_FIFO; + lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; + lis.cfg.fifo.size = 15; /* size must be < 32 to use the watermark interrupt */ + + /* write cfg to device */ + if (lis3dh_configure(&lis)) { + /* error handling */ + } + + for ( ;; ) { + + /* wait until FIFO overrun interrupt is active */ + if (int_poll(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + /* read FIFO into `fifo_data' struct `fifo' */ + if (lis3dh_read_fifo(&lis, &fifo)) { + /* error handling */ + } + + /* print data .. */ + for(i=0; i /* usleep() */ +#include +#include "lis3dh.h" +#include "i2c.h" + +int main() { + + lis3dh_t lis; + struct lis3dh_fifo_data fifo; + int i; + + lis.dev.init = i2c_init; + lis.dev.read = i2c_read; + lis.dev.write = i2c_write; + lis.dev.sleep = usleep; + lis.dev.deinit = i2c_deinit; + + /* initialise struct and check device id */ + if (lis3dh_init(&lis)) { + /* error handling */ + } + + /* reset just in case*/ + if (lis3dh_reset(&lis)) { + /* error handling */ + } + + lis.cfg.mode = LIS3DH_MODE_HR; + lis.cfg.range = LIS3DH_FS_2G; + lis.cfg.rate = LIS3DH_ODR_100_HZ; + lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_FIFO; + + /* modifying the size of the FIFO buffer is not useful when just polling without interrupts */ + + /* write cfg to device */ + if (lis3dh_configure(&lis)) { + /* error handling */ + } + + for ( ;; ) { + + /* read FIFO into `fifo_data' struct `fifo' */ + if (lis3dh_read_fifo(&lis, &fifo)) { + /* error handling */ + } + + /* print data .. */ + for(i=0; i /* usleep() */ +#include +#include "lis3dh.h" +#include "i2c.h" +#include "interrupt.h" + +/* Raspberry Pi GPIO pin connected to LIS3DH INT1 pin */ +#define GPIO_INTERRUPT_PIN_INT1 12 + +int main() { + + lis3dh_t lis; + struct lis3dh_fifo_data fifo; + int i; + + lis.dev.init = i2c_init; + lis.dev.read = i2c_read; + lis.dev.write = i2c_write; + lis.dev.sleep = usleep; + lis.dev.deinit = i2c_deinit; + + /* initialise struct and check device id */ + if (lis3dh_init(&lis)) { + /* error handling */ + } + + /* reset just in case*/ + if (lis3dh_reset(&lis)) { + /* error handling */ + } + + /* register interrupt */ + if (int_register(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + lis.cfg.mode = LIS3DH_MODE_HR; + lis.cfg.range = LIS3DH_FS_2G; + lis.cfg.rate = LIS3DH_ODR_100_HZ; + lis.cfg.pin1.overrun = 1; + lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM; + lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; + + /* write cfg to device */ + if (lis3dh_configure(&lis)) { + /* error handling */ + } + + for ( ;; ) { + + /* wait until FIFO overrun interrupt is active */ + if (int_poll(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + /* read FIFO into `fifo_data' struct `fifo' */ + if (lis3dh_read_fifo(&lis, &fifo)) { + /* error handling */ + } + + /* print data .. */ + for(i=0; i /* usleep() */ +#include +#include "lis3dh.h" +#include "i2c.h" +#include "interrupt.h" + +/* Raspberry Pi GPIO pin connected to LIS3DH INT1 pin */ +#define GPIO_INTERRUPT_PIN_INT1 12 + +int main() { + + lis3dh_t lis; + struct lis3dh_fifo_data fifo; + int i; + + lis.dev.init = i2c_init; + lis.dev.read = i2c_read; + lis.dev.write = i2c_write; + lis.dev.sleep = usleep; + lis.dev.deinit = i2c_deinit; + + /* initialise struct and check device id */ + if (lis3dh_init(&lis)) { + /* error handling */ + } + + /* reset just in case*/ + if (lis3dh_reset(&lis)) { + /* error handling */ + } + + /* register interrupt */ + if (int_register(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + lis.cfg.mode = LIS3DH_MODE_HR; + lis.cfg.range = LIS3DH_FS_2G; + lis.cfg.rate = LIS3DH_ODR_100_HZ; + lis.cfg.pin1.wtm = 1; /* watermark interrupt */ + lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM; + lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; + lis.cfg.fifo.size = 15; /* size must be < 32 to use the watermark interrupt */ + + /* write cfg to device */ + if (lis3dh_configure(&lis)) { + /* error handling */ + } + + for ( ;; ) { + + /* wait until FIFO overrun interrupt is active */ + if (int_poll(GPIO_INTERRUPT_PIN_INT1)) { + /* error handling */ + } + + /* read FIFO into `fifo_data' struct `fifo' */ + if (lis3dh_read_fifo(&lis, &fifo)) { + /* error handling */ + } + + /* print data .. */ + for(i=0; i /* usleep() */ +#include +#include "lis3dh.h" +#include "i2c.h" + +int main() { + + lis3dh_t lis; + struct lis3dh_fifo_data fifo; + int i; + + lis.dev.init = i2c_init; + lis.dev.read = i2c_read; + lis.dev.write = i2c_write; + lis.dev.sleep = usleep; + lis.dev.deinit = i2c_deinit; + + /* initialise struct and check device id */ + if (lis3dh_init(&lis)) { + /* error handling */ + } + + /* reset just in case*/ + if (lis3dh_reset(&lis)) { + /* error handling */ + } + + lis.cfg.mode = LIS3DH_MODE_HR; + lis.cfg.range = LIS3DH_FS_2G; + lis.cfg.rate = LIS3DH_ODR_100_HZ; + lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM; + + /* modifying the size of the FIFO buffer is not useful when just polling without interrupts */ + + /* write cfg to device */ + if (lis3dh_configure(&lis)) { + /* error handling */ + } + + for ( ;; ) { + + /* read FIFO into `fifo_data' struct `fifo' */ + if (lis3dh_read_fifo(&lis, &fifo)) { + /* error handling */ + } + + /* print data .. */ + for(i=0; i