fix reg order and longer sleep after configure(). Amend notes on usage
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@ -1,5 +0,0 @@
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SPI does not work properly
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-- writes may go to wrong addr
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-- FIFO read out addr 6 loop seems to not work
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FIFO WTM/OVRN on INT1 does not fire when FTH (watermark) is not 31 (default/max)
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@ -21,7 +21,7 @@ See the `examples/` dir for complete code examples
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## Implementation
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This driver requires the user to implement the following interface functions:
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This project has example interface code for I2C and SPI used on Raspberry Pi 4.
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This project has example interface code for I2C and SPI used on Raspberry Pi 4, and for STM32.
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```c
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/* initialise the "interface" */
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int init(void);
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@ -40,8 +40,7 @@ If `init` and/or `deinit` are set to `NULL`, they will be ignored. Useful on mic
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---
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### Using i2c on STM32
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Example code because I couldn't previously find working examples.
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### STM32
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```c
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#define LIS3DH_I2C_ADDR 0x18
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@ -4,10 +4,12 @@
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Basic example of how to use this device
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### file: fifo.c
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Instead of polling for every single [x y z] set, a FIFO with programmable capacity ("watermark") can be used, and then dumped into memory once full. All FIFO readings use 10-bit resolution regardless of the mode set in `lis.cfg.mode`. The watermark level can be adjusted to a value [1-32] (0 disables FIFO) by modifying the `lis.cfg.fifo.size` property before calling `lis3dh_configure()`.
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Instead of polling for every single [x y z] set, a FIFO with programmable capacity ("watermark") can be used, and then dumped into memory once full. All FIFO readings use 10-bit resolution regardless of the mode set in `cfg.mode`. The watermark level can be adjusted to a value [1-32] (0 disables FIFO) by modifying the `cfg.fifo.size` property before calling `lis3dh_configure()`.
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The LIS3DH can optionally apply a HP filter on the sampling to reduce 'static acceleration' from the data.
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Note: `pin1.wtm` will NOT trigger if the FIFO size is 32 (default). Use `pin1.overrun` if you want an interrupt when the FIFO is full at full size (32.)
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### file: interrupts.c
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This device supports two different interrupt "output pins," `INT1` and `INT2`. The appropriate flag must be set in either `cfg.pin1` or `cfg.pin2` and the interrupt source must be configured to trigger into `INT1` or `INT2`.
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@ -42,8 +42,7 @@ int main() {
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lis.cfg.rate = LIS3DH_ODR_100_HZ;
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lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM;
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lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; /* trigger interrupt into int pin1 */
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/*lis.cfg.fifo.size = 15;*/
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lis.cfg.pin1.wtm = 1; /* trigger upon FIFO watermark level reached */
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lis.cfg.pin1.overrun = 1; /* trigger upon FIFO overrun */
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/* set up HP filter to remove DC component */
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lis.cfg.filter.mode = LIS3DH_FILTER_MODE_NORMAL_REF;
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14
lis3dh.c
14
lis3dh.c
@ -147,7 +147,7 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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fifo_ctrl_reg |= ((lis3dh->cfg.fifo.trig & 1) << 5);
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}
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/* set enable filter */
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/* set enable filter if mode is set */
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if (lis3dh->cfg.filter.mode != 0xFF) {
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ctrl_reg2 |= ((lis3dh->cfg.filter.mode & 0x03) << 6);
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ctrl_reg2 |= ((lis3dh->cfg.filter.cutoff & 0x03) << 4);
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@ -175,9 +175,10 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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ctrl_reg0 |= 0x10;
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ctrl_reg0 |= (lis3dh->cfg.sdo_pullup & 1) << 7;
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/* Registers have to be set in this order for SPI to function correctly */
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err |= lis3dh->dev.write(REG_CTRL_REG4, ctrl_reg4);
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err |= lis3dh->dev.write(REG_CTRL_REG5, ctrl_reg5);
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err |= lis3dh->dev.write(REG_FIFO_CTRL_REG, fifo_ctrl_reg);
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err |= lis3dh->dev.write(REG_INT1_CFG, int1_cfg);
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err |= lis3dh->dev.write(REG_INT1_THS, int1_ths);
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@ -194,16 +195,13 @@ int lis3dh_configure(lis3dh_t *lis3dh) {
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err |= lis3dh->dev.write(REG_ACT_DUR, lis3dh->cfg.act_dur);
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err |= lis3dh->dev.write(REG_TEMP_CFG_REG, temp_cfg_reg);
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err |= lis3dh->dev.write(REG_REFERENCE, lis3dh->cfg.reference);
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err |= lis3dh->dev.write(REG_CTRL_REG1, ctrl_reg1);
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err |= lis3dh->dev.write(REG_CTRL_REG6, ctrl_reg6);
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err |= lis3dh->dev.write(REG_CTRL_REG0, ctrl_reg0);
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err |= lis3dh->dev.write(REG_CTRL_REG2, ctrl_reg2);
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err |= lis3dh->dev.write(REG_CTRL_REG3, ctrl_reg3);
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err |= lis3dh->dev.write(REG_CTRL_REG1, ctrl_reg1);
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/* sleep for a period TBD ~ ODR */
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lis3dh->dev.sleep(1000); /* 50 ms */
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lis3dh->dev.sleep(100000); /* 100 ms */
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return err;
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}
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@ -257,7 +255,7 @@ static uint8_t acc_sensitivity(uint8_t mode, uint8_t range) {
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}
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}
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/* read a single [x y z] set. Assume configured and poll'd */
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int lis3dh_read(lis3dh_t *lis3dh) {
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uint8_t data[6];
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uint8_t shift, sens;
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73
main.c
73
main.c
@ -1,14 +1,19 @@
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#define _GNU_SOURCE
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#include <unistd.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <math.h>
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#include "lis3dh.h"
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#include "i2c.h"
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#include "interrupt.h"
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#include "spi.h"
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/* GPIO 12 or Pin 32 */
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#define GPIO_INTERRUPT_PIN 12
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int main() {
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lis3dh_t lis;
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struct lis3dh_fifo_data data;
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struct lis3dh_fifo_data fifo;
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int i;
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lis.dev.init = spi_init;
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@ -17,49 +22,67 @@ int main() {
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lis.dev.sleep = usleep;
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lis.dev.deinit = spi_deinit;
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/* initialise LIS3DH struct */
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/* initalise LIS3DH struct */
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if (lis3dh_init(&lis)) {
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puts("init()");
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/* error handling */
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}
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/* reset device just in case */
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if (lis3dh_reset(&lis)) {
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puts("reset()");
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/* error handling */
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}
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lis.cfg.mode = LIS3DH_MODE_HR;
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/* register interrupt */
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if (int_register(GPIO_INTERRUPT_PIN)) {
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/* error handling */
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}
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lis.cfg.mode = LIS3DH_MODE_NORMAL;
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lis.cfg.range = LIS3DH_FS_2G;
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lis.cfg.rate = LIS3DH_ODR_400_HZ;
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lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM_TO_FIFO;
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lis.cfg.fifo.size = 20;
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lis.cfg.rate = LIS3DH_ODR_100_HZ;
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lis.cfg.fifo.mode = LIS3DH_FIFO_MODE_STREAM;
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lis.cfg.fifo.trig = LIS3DH_FIFO_TRIG_INT1; /* trigger interrupt into int pin1 */
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lis.cfg.pin1.overrun = 1; /* trigger upon FIFO overrun */
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/* set up HP filter to remove DC component */
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lis.cfg.filter.mode = LIS3DH_FILTER_MODE_NORMAL_REF;
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lis.cfg.filter.cutoff = LIS3DH_FILTER_CUTOFF_4;
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lis.cfg.filter.fds = 1; /* remove this line, or set to 1 to enable filter */
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/* write device config */
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if (lis3dh_configure(&lis)) {
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puts("configure()");
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/* error handling */
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}
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A:
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/* poll fifo register until it reports that the watermark level has
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been reached, or that it has overwritten old data, whichever
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happens first. */
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if (lis3dh_poll_fifo(&lis)) {
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puts("poll_fifo()");
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/* read REFERENCE to set filter to current accel field */
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if (lis3dh_reference(&lis)) {
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/* error handling */
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}
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/* wait for interrupt from LIS3DH */
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if (int_poll(GPIO_INTERRUPT_PIN)) {
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/* error handling */
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}
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/* read as many [x y z] sets as specified by watermark level (fth) */
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/* copy them to the fifo data struct given below as `fifo' */
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if (lis3dh_read_fifo(&lis, &data)) {
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puts("read_fifo()");
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if (lis3dh_read_fifo(&lis, &fifo)) {
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/* error handling */
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}
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/* read out fifo buffer data */
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for(i=0; i<data.size; i++) {
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printf("x: %d mg, y: %d mg, z: %d mg\n", data.x[i], data.y[i], data.z[i]);
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/* above function also writes out the qty of [x y z] sets stored in `fifo' */
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for(i=0; i<fifo.size; i++) {
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printf("x: %d mg, y: %d mg, z: %d mg\n", fifo.x[i], fifo.y[i], fifo.z[i]);
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}
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goto A;
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/* deinitialise struct */
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/* unregister interrupt */
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if (int_unregister(GPIO_INTERRUPT_PIN)) {
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/* error handling */
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}
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/* deinitalise struct */
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if (lis3dh_deinit(&lis)) {
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puts("deinit()");
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/* error handling */
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}
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return 0;
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