From fa105d9d3f6bbe0e9e4028a71756bd3afa771ce2 Mon Sep 17 00:00:00 2001 From: Robin Date: Fri, 19 Feb 2010 15:10:11 +0000 Subject: [PATCH] more chapters from cvs --- sw_as_plds/ir_det_pld.dia | 751 ++++++++++++++++++++++++++++++++++++++ sw_as_plds/sw_as_plds.tex | 169 +++++++++ thesis.tex | 4 +- 3 files changed, 922 insertions(+), 2 deletions(-) create mode 100644 sw_as_plds/ir_det_pld.dia create mode 100644 sw_as_plds/sw_as_plds.tex diff --git a/sw_as_plds/ir_det_pld.dia b/sw_as_plds/ir_det_pld.dia new file mode 100644 index 0000000..63227d6 --- /dev/null +++ b/sw_as_plds/ir_det_pld.dia @@ -0,0 +1,751 @@ + + + + + + + + + + + + + #A4# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #main# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ## + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #while(1)# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.1 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.2 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.3 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #ir_self_test# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.4.1 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.4.2 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #¬ir_self_test# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #ir_detected# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #¬ir_detected# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.4.2.1 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.4.2.2 *# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ##1.5.1 *# + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sw_as_plds/sw_as_plds.tex b/sw_as_plds/sw_as_plds.tex new file mode 100644 index 0000000..4a4719f --- /dev/null +++ b/sw_as_plds/sw_as_plds.tex @@ -0,0 +1,169 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% $Id: sw_as_plds.tex,v 1.2 2008/11/04 07:40:50 robin Exp $ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% +%%\documentclass{entcs} \usepackage{formatmacro} \usepackage{epsfig} \usepackage{pspicture} \usepackage{pstricks} \usepackage{subfigure} \usepackage{tikz} +%\documentclass{entcs} \usepackage{formatmacro} \usepackage{epsfig} \usepackage{pstricks} \usepackage{subfigure} \usepackage{tikz} +% +%\newcommand{\Fam}{{\mathbb F}} +%\newcommand{\Pow}{{\mathbb P}} +%\newcommand{\Dis}{{\vee}} +%\newcommand{\Con}{{\wedge}} +%\newcommand{\FMEA}{{\bowtie}} +% +%\newcommand{\Nat}{{\mathbb N}} +%\newcommand{\Real}{{\mathbb R}} +%\newcommand{\Complex} {{\mathbb C}} +%\newcommand{\Rational} {{\mathbb Q}} +% +%%\bibliographystyle{unsrt} +%%\newtheorem{theorem}{Thoeorem} +% +%\def\lastname{Clark} +%\begin{document} +%\begin{frontmatter} +% \title{ Software Component Failure Analysis } \author{Robin Clark\thanksref{ALL}\thanksref{r.clark@energytechnologycontrol.com}} +% \address{ Energy Technology Control\\ +% 25 North Street, Lewes, BN7 2PE, Great Britain} +% +\begin{abstract} +This chapter describes how software can be represented by first order logic, and how +software elements be represented in a propositional logic diagram. +When represented in this way they can be combined with other PLD's representing hardware and mechanical elements. +Thus, Fault Mode Effects Analysis (FMEA) can be applied to electro/software/mechanical systems +using a common mathematically based formal graphical notation. +\end{abstract} + +% +%\begin{keyword} +% fault~tree fault~mode EN298 EN61508 EN12067 EN230 UL1998 safety~critical logic euler venn propositional +%\end{keyword} +%\end{frontmatter} +% + +\section{Introduction} + +The code in software defines logical euations and these determine the flow, or path software takes though the code. +Because computer languages are very well defined, they can be viewed as formal languages. +Becuase of this, they can be mapped onto propositional logic. + +Software can be viewed in terms of program flow stages. +Transitioning between one stage and another depends on decisions made from +variable states. This corresponds to the standard software structures, if-then-else + do-while etc. + +At a program flow stage, the software may initiate actions. Typically, in an embedded +system, a micro controller will read from external sensors, and then apply +outputs to control the equipment under supervision. + +Each test case in a PLD software diagram, corresponds to an action +taken by the software. This action could be to modify an internal flag or variable, +or it could be modify an output that can actuate an action outside the micro-controller. + +A simple example illustrates this, a simple micro-controller program, +that reads an IR detector and then displays status on a bank of LEDs. +Also that it has a self test IR LED, and a mechanical shutter +to prove the detector can determine dark IR conditions. + + +\clearpage +\begin{verbatim} + // example C code + + main () { + + // program flow point main #1 + set_up_microcontroller_hardware(); + + while ( 1 ) { + + // program flow point main #1.1 + delay(20 milli seconds); + + // program flow point main #1.2 + self_test(); + + // program flow point main #1.3 + read_inputs(); + + // program flow point main #1.4 + if ( ir_self_test_passed ) { + + // program flow point main #1.4.1 + flash_green_led(); + + // program flow point main #1.4.2 + if ( ir_detected ) + // program flow point main #1.4.2.1 + flash_yellow_led(); + else + // program flow point main #1.4.2.2 + flash_blue_led(); + } + // program flow point main #1.5 + else { + // program flow point main #1.5.1 + flash_red_led(); // indicate internal ERROR + } + + } +\end{verbatim} + +\clearpage +% +% \begin{figure}[h+] +% \includegraphics[scale=0.40]{sw_as_plds/ir_det_pld.eps} +% \caption{} +% \label{fig:ir_det_pld} +% \end{figure} % OR + +\begin{figure}[h] + \centering + \includegraphics[width=400pt,bb=0 0 675 1023,keepaspectratio=true]{sw_as_plds/ir_det_pld.png} + % ir_det_pld.png: 675x1023 pixel, 72dpi, 23.81x36.09 cm, bb=0 0 675 1023 + \caption{IR Detector C code as PLD} + \label{fig:ir_det_pld} +\end{figure} + + +Note that the function calls in the example code, will +each create their own PLD diagram, which can be considered as being nested in +the main diagram. + +{\huge DIAGRAM REQUIRED OF NESTED DIAGRAMS FOR FUNCTION CALLS} +Note it should be possible to automatically generate +diagrams from code. +Analyse C code for instance and make these types of diagrams. + +\subsection{Afferent, processing and Efferent flow} + +A concept from Yourdon dataflow analysis, is that there +is Afferent, processing and Efferent flow. +That is to say information comes in (afferent flow) +is processed and the actions or data out, are the efferent flow. + +In a real time system, this corresponds to a hierarchy where +electrical and mechanical systems sit at either end with the +computer providing the processing. re-phrase. + +Need tree diagram here with MECH as lowest, electronics and then SW +as typical program structure. +{\huge DIAGRAM REQUIRED} +\clearpage + +%%\bibliography{vmgbibliography,mybib} +% +% +%Typeset in \ \ {\huge \LaTeX} \ \ on \ \ \today +% +%\begin{verbatim} +%CVS Revision Identity $Id: sw_as_plds.tex,v 1.2 2008/11/04 07:40:50 robin Exp $ +%\end{verbatim} +%Compiled last \today +%\end{document} +% +%\theend +% +% +% diff --git a/thesis.tex b/thesis.tex index 4dbe824..75ac74c 100644 --- a/thesis.tex +++ b/thesis.tex @@ -65,11 +65,11 @@ \typeout{ ---------------- Electronic Components as PLDs} \chapter {Electronic Components as PLDs} -%\input {components_as_plds/components_as_plds} +\input {components_as_plds/components_as_plds} \typeout{ ---------------- Software as PLDs} \chapter {Software as PLDs} -%\input{sw_as_plds/sw_as_plds} +\input{sw_as_plds/sw_as_plds} \typeout{ ---------------- Mechanical Sub-systems as PLDs} \chapter {Mechanical Sub-systems as PLDs}