diff --git a/submission_thesis/CH5_Examples/Makefile b/submission_thesis/CH5_Examples/Makefile index db91feb..a977c7c 100644 --- a/submission_thesis/CH5_Examples/Makefile +++ b/submission_thesis/CH5_Examples/Makefile @@ -5,7 +5,7 @@ PNG_DIA = blockdiagramcircuit2.png bubba_oscillator_block_diagram.png circuit1 poss1finalbubba.png poss2finalbubba.png pt100.png pt100_doublef.png pt100_singlef.png \ pt100_tc.png pt100_tc_sp.png shared_component.png stat_single.png three_tree.png \ tree_abstraction_levels.png vrange.png sigma_delta_block.png ftcontext.png ct1.png hd.png \ - sigdel1.png sdadc.png bubba_euler_1.png bubba_euler_2.png + sigdel1.png sdadc.png bubba_euler_1.png bubba_euler_2.png eulersd.png diff --git a/submission_thesis/CH5_Examples/bubba_euler_2.dia b/submission_thesis/CH5_Examples/bubba_euler_2.dia index 35d3547..aaaa3c5 100644 Binary files a/submission_thesis/CH5_Examples/bubba_euler_2.dia and b/submission_thesis/CH5_Examples/bubba_euler_2.dia differ diff --git a/submission_thesis/CH5_Examples/copy.tex b/submission_thesis/CH5_Examples/copy.tex index cac68f0..4c18ff8 100644 --- a/submission_thesis/CH5_Examples/copy.tex +++ b/submission_thesis/CH5_Examples/copy.tex @@ -1457,8 +1457,9 @@ could be easily detected; the failure symptom $FilterIncorrect$ may be less obs This circuit is described in the Analog Applications Journal~\cite{bubba}[p.37]. The circuit implements an oscillator using four 45 degree phase shifts, and an inverting amplifier to provide -gain and the final 180 degrees of phase shift (making a total of 360 degrees of phase shift). - +gain and the final 180 degrees of phase shift (making a total of 360). % degrees of phase shift). +The circuit provides two outputs with a quadrature phase relationship. +% From a fault finding perspective this circuit cannot be de-composed because the whole circuit is enclosed within a feedback loop. However, this is not a problem for FMMD, as {\fgs} are readily identifiable. The signal path is circular (its a positive feedback circuit) and most failures would simply cause the output to stop oscillating. @@ -1546,7 +1547,7 @@ $$ CC(NIBUFF) = 0 $$ \subsection{Bringing the functional Groups Together: FMMD model of the `Bubba' Oscillator.} We could at this point bring all the {\dcs} together into one large functional -group (see figure~\ref{fig:poss1finalbubba}) +group (see figure~\ref{fig:bubbaeuler1}) %{fig:poss1finalbubba}) or we could try to merge smaller stages. Initially we use the first identified {\fgs} to create our model without further stages of refinement/hierarchy. @@ -1555,9 +1556,9 @@ Initially we use the first identified {\fgs} to create our model without further \subsection{FMMD Analysis using initially identified functional groups} Our functional group for this analysis can be expressed thus: -or in Euler diagram format as in figure~\ref{fig:bubbaeuler1}. +% $$ G^1_0 = \{ PHS45^1_1, NIBUFF^0_1, PHS45^1_2, NIBUFF^0_2, PHS45^1_3, NIBUFF^0_3 PHS45^1_4, INVAMP^1_0 \} ,$$ - +or in Euler diagram format as in figure~\ref{fig:bubbaeuler1}. % HTR 23SEP2012 \begin{figure}[h+] % HTR 23SEP2012 \centering % HTR 23SEP2012 \includegraphics[width=300pt,keepaspectratio=true]{CH5_Examples/poss1finalbubba.png} @@ -1565,7 +1566,7 @@ $$ G^1_0 = \{ PHS45^1_1, NIBUFF^0_1, PHS45^1_2, NIBUFF^0_2, PHS45^1_3, NIBUFF^0 % HTR 23SEP2012 \caption{Bubba Oscillator: One large functional group using the initial functional groups to model oscillator.} % HTR 23SEP2012 \label{fig:poss1finalbubba} % HTR 23SEP2012 \end{figure} - +% \begin{figure}[h] \centering \includegraphics[width=400pt]{./CH5_Examples/bubba_euler_1.png} @@ -1573,7 +1574,7 @@ $$ G^1_0 = \{ PHS45^1_1, NIBUFF^0_1, PHS45^1_2, NIBUFF^0_2, PHS45^1_3, NIBUFF^0 \caption{Euler diagram showing the hierarchy of the initial FMMD analysis performed on the Bubba Oscillator circuit.} \label{fig:bubbaeuler1} \end{figure} - +% \begin{table}[h+] \caption{Bubba Oscillator: Failure Mode Effects Analysis: One Large Functional Group} % title of Table \label{tbl:bubbalargefg} @@ -1632,17 +1633,17 @@ $$ G^1_0 = \{ PHS45^1_1, NIBUFF^0_1, PHS45^1_2, NIBUFF^0_2, PHS45^1_3, NIBUFF^0 Collecting symptoms from table~\ref{tbl:bubbalargefg} we can show that for single failure modes, applying $fm$ to the bubba oscillator returns three failure modes, - +% $$ fm(BubbaOscillator) = \{ NO_{osc}, HI_{fosc}\} . $$ %, LO_{fosc} \} . $$ - +% %For the final stage of this FMMD model, we can calculate the complexity using equation~\ref{eqn:rd2}. %$$ CC = 28 \times 8 = 224$$ - +% %To obtain the total comparison complexity ($TCC$), we need to add the complexity from the %{\dcs} that $BubbaOscillator$ was built from. - +% %$$ TCC = 28 \times 8 + 4 \times 4 + 4 \times 0 + 10 = 250$$ - +% %As we have re-used the analysis for BUFF45 we could even reasonably remove %$3 \times 4=12$ from this result, because the results from $BUFF45$ have been used four times. %Traditional FMEA would have lead us to a much higher comparison complexity @@ -1659,7 +1660,7 @@ we may also discover new derived components that may be of use for other analyse \clearpage -\subsection{FMMD Analysis of Bubba Oscillator using more hierarchical stages} +\subsection{FMMD Analysis of Bubba Oscillator using a finer grained modular approach (i.e. more hierarchical stages)} The example above---from the initial {\fgs}---used one very large functional group to model the circuit. %This mean a quite large comparison complexity for this final stage. @@ -1688,28 +1689,25 @@ We take the $NIBUFF$ and $PHS45$ and with those three, form a $PHS135BUFFERED$ functional group. $PHS135BUFFERED$ is a {\dc} representing an actively buffered $135^{\circ}$ phase shifter. - +% A PHS45 {\dc} and an inverting amplifier\footnote{Inverting amplifiers always apply a $180^{\circ}$ phase shift.}, form a {\fg} providing an amplified $225^{\circ}$ phase shift, which we can call $PHS225AMP$. - +% %---with the remaining $PHS45$ and the $INVAMP$ (re-used from section~\ref{sec:invamp})in a second group $PHS225AMP$--- -Finally we can merge $PHS135BUFFERED$ and $PHS225AMP$ in a final stage (see figure~\ref{fig:poss2finalbubba}) - - - +Finally we can merge $PHS135BUFFERED$ and $PHS225AMP$ in a final stage (see figure~{fig:bubbaeuler2}) % \ref{fig:poss2finalbubba}) +% %We can take a more modular approach by creating two intermediate functional groups, a buffered $45^{\circ}$ phase shifter (BUFF45) %we can combine three $BUFF45$'s to make %a $135^{\circ}$ buffer phase shifter (PHS135BUFFERED). - +% %We can combine a $PHS45$ and a $NIBUFF$ to create %and an amplifying $225^{\circ}$ phase shifter (PHS225AMP). - +% % By combining PHS225AMP and PHS135BUFFERED we can create a more modularised hierarchical % model of the bubba oscillator. % The proposed hierarchy is shown in figure~\ref{fig:poss2finalbubba}. - - +% \begin{table}[h+] \caption{BUFF45: Failure Mode Effects Analysis} % title of Table \label{tbl:buff45} @@ -1732,18 +1730,16 @@ Finally we can merge $PHS135BUFFERED$ and $PHS225AMP$ in a final stage (see fig \end{tabular} \end{table} - - +% Collecting symptoms from table~\ref{tbl:buff45}, we can create a derived component $BUFF45$ which has the following failure modes: $$ fm (BUFF45) = \{ 0\_phaseshift, NO\_signal .\} % 90\_phaseshift, $$ - +% %$$ CC(BUFF45) = 7 \times 1 = 7 $$ - +% We can now combine three $BUFF45$ {\dcs} and create a $PHS135BUFFERED$ {\dc}. - - +% \begin{table}[h+] \caption{PHS135BUFFERED: Failure Mode Effects Analysis} % title of Table \label{tbl:phs135buffered} @@ -1770,20 +1766,20 @@ We can now combine three $BUFF45$ {\dcs} and create a $PHS135BUFFERED$ {\dc}. \end{tabular} \end{table} - - +% +% Collecting symptoms from table~\ref{tbl:phs135buffered}, we can create a derived component $PHS135BUFFERED$ which has the following failure modes: $$ fm (PHS135BUFFERED) = \{ 90\_phaseshift, NO\_signal .\} % 180\_phaseshift, $$ - - +% +% %$$ CC (PHS135BUFFERED) = 3 \times 2 = 6 $$ - - - +% +% +% The $PHS225AMP$ consists of a $PHS45$ and an $INVAMP$ (which provides $180^{\circ}$ of phase shift). - +% \begin{table}[h+] \caption{PHS225AMP: Failure Mode Effects Analysis} % title of Table \label{tbl:phs225amp} @@ -1805,21 +1801,21 @@ The $PHS225AMP$ consists of a $PHS45$ and an $INVAMP$ (which provides $180^{\cir \end{tabular} \end{table} - +% Collecting symptoms from table~\ref{tbl:phs225amp}, we can create a derived component $PHS225AMP$ which has the following failure modes: $$ fm (PHS225AMP) = \{ 180\_phaseshift, NO\_signal .\} % 270\_phaseshift, $$ - +% %$$ CC(PHS225AMP) = 7 \times 1 $$ - +% The $PHS225AMP$ consists of a $PHS45$ and an $INVAMP$ (which provides $180^{\circ}$ of phase shift). - - - +% +% +% To complete the analysis we now bring the derived components $PHS135BUFFERED$ and $PHS225AMP$ together and perform FMEA with these. - +% \begin{table}[h+] \caption{BUBBAOSC: Failure Mode Effects Analysis} % title of Table \label{tbl:bubba2} @@ -1841,18 +1837,17 @@ and perform FMEA with these. \end{tabular} \end{table} - - +% Collecting symptoms from table~\ref{tbl:bubba2}, we can create a derived component $BUBBAOSC$ which has the following failure modes: $$ fm (BUBBAOSC) = \{ HI_{osc}, NO\_signal .\} % LO_{fosc}, $$ - +% %We could trace the DAGs here and ensure that both analysis strategies worked ok..... - +% %$$ CC(BUBBAOSC) = 6 \times (2-1) = 6 $$ - - +% +% % We can now add the comparison complexities for all levels of the analysis represented in figure~\ref{fig:poss2finalbubba}. % We have at the lowest level two $PHS45$ {\dcs} giving a CC of 8 and $INVAMP$ with a CC of 10, % at the next level four $BUFF45$ {\dcs} giving $(4-1).7=21$, @@ -1864,10 +1859,10 @@ $$ It has %also given us five {\dcs}, building blocks, which could potentially be re-used for similar circuitry to analyse in the future. - - +% +% \subsection{Comparing both approaches} - +% %In general with large functional groups the comparison complexity %is higher, by an order of $O(N^2)$. Smaller functional groups mean less by-hand checks are required. @@ -1875,9 +1870,21 @@ It also means a more finely grained model. This means that there are more {\dcs} and this increases the possibility of re-use. % HTR The more we can modularise, the more we decimate the $O(N^2)$ effect % HTR of complexity comparison. +% + +\clearpage -\section{Sigma Delta Analogue to Digital Converter.} %($\Sigma \Delta ADC$)} + + + + + + + + + +\section{Sigma Delta Analogue to Digital Converter ($\Sigma \Delta ADC$).} %($\Sigma \Delta ADC$)} \label{sec:sigmadelta} The following example is used to demonstrate FMMD analysis of a mixed analogue and digital circuit (see figure~\ref{fig:sigmadelta}). \begin{figure}[h] @@ -1887,18 +1894,16 @@ The following example is used to demonstrate FMMD analysis of a mixed analogue a \caption{Sigma Delta Analogue to Digital Converter} \label{fig:sigmadelta} \end{figure} - - - +% \nocite{f77} \nocite{sccs} \nocite{electronicssysapproach} - +% \begin{figure}[h] \centering \includegraphics[width=200pt,keepaspectratio=true]{./CH5_Examples/sigma_delta_block.png} % sigma_delta_block.png: 828x367 pixel, 72dpi, 29.21x12.95 cm, bb=0 0 828 367 - \caption{Sigma Delta ADC signal path} + \caption{Electrical signal path Block diagram: $\Sigma \Delta ADC$} % Analogue to Digital Converter } \label{fig:sigmadeltablock} \end{figure} @@ -1929,36 +1934,40 @@ and fed into the summing integrator completing the negative feedback loop. \subsection{FMMD analysis of \sd } The partslist for the \sd : - +% $$\{ IC1, IC2, IC3, IC4, R1, R2, R3, R4, C1 \} $$. - +% IC1,2 and 3 are all Op-amps and we have failure modes from section~\ref{sec:opampfm}. - +% $$ fm(OPAMP) = \{ HIGH, LOW, NOOP, LOW\_SLEW \} $$ - +% We examine the literature for a failure model for the D-type flip flop~\cite{fmd91}[3-105], the CD4013B~\cite{cd4013Bds}, and obtain its failure modes, which we can express using the $fm$ function: - +%% $$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$ - +% The resistors and capacitor failure modes we take from EN298~\cite{en298}[An.A] - +% $$ fm ( R ) = \{OPEN, SHORT\} $$ - - +% $$ fm ( C ) = \{OPEN, SHORT\} $$ - +% +We are also given a CLOCK. For the purpose of example we shall attribute +one failure mode to this, that it might stop. +% +$$ fm ( CLOCK ) = \{ STOPPED \} $$ \subsection{Identifying initial {\fgs}} -\subsubsection{Summing Junction} +\subsubsection{Summing Junction Integrator (SUMJINT)} We now need to choose {\fgs}. The signal path is circular, but we can start with the input voltage, which is applied via $R2$, we term this voltage $V_{in}$. % The feedback voltage for the ADC is supplied via $R1$, we term this voltage as $V_{fb}$. %The input voltage is supplied via $R2$ and we term this voltage as $V_{in}$. -$R2$ and $R1$ form a summing junction to IC1: they thus work to fulfil this specific function. -This can be our first {\fg} and we analyse it in table~\ref{tbl:suml=j}. +$R2$ and $R1$ form a summing junction to IC1: they balance the integrator provided +by the capacitor C1 and the opamp IC1. +This can be our first {\fg} and we analyse it in table~\ref{tbl:sumjint}. %For the symptoms, we have to think in terms of the effect %on its performance as a summing junction and not be %distracted by the integrator formed by $C_1$ and $IC1$. @@ -1967,8 +1976,8 @@ $$G^0_1 = \{R1, R2 \}$$ \begin{table}[h+] \center -\caption{R1,R2 Summing Junction: Failure Mode Effects Analysis} % title of Table -\label{tbl:sumj} +\caption{ Summing Junction Integrator: Failure Mode Effects Analysis} % title of Table +\label{tbl:sumjint} \begin{tabular}{|| l | l | c | c | l ||} \hline \textbf{Failure Scenario} & & \textbf{failure result} & & \textbf{Symptom} \\ @@ -1978,74 +1987,111 @@ $$G^0_1 = \{R1, R2 \}$$ FS2: $R1$ $SHORT$ & & $V_{fb}$ dominates input & & $V_{fb} DOM$ \\ \hline FS3: $R2$ $OPEN$ & & $V_{fb}$ dominates input & & $V_{fb} DOM$ \\ FS4: $R2$ $SHORT$ & & $V_{in}$ dominates input & & $V_{in} DOM$ \\ \hline + FS5: $IC1$ $HIGH$ & & output perm. high & & HIGH \\ + FS6: $IC1$ $LOW$ & & output perm. low & & LOW \\ \hline + FS7: $IC1$ $NOOP$ & & no current to drive C1 & & NO\_INTEGRATION \\ + FS8: $IC1$ $LOW\_SLEW$ & & signal delay to C1 & & NO\_INTEGRATION \\ \hline + FS9: $C1$ $OPEN$ & & no capacitance & & NO\_INTEGRATION \\ + FS10: $C1$ $SHORT$ & & no capacitance & & NO\_INTEGRATION \\ \hline + +% \hline +% FS1: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ +% FS2: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline +% FS3: $IC2$ $NOOP$ & & no current drive & & LOW \\ +% FS4: $IC2$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline +% \hline \hline - \end{tabular} \end{table} +% +% +% \end{tabular} +% \end{table} From the analysis in table~\ref{tbl:sumj} we collect symptoms. We can create the derived component -$SUMJ$.% which has the failure modes from collecting its symptoms. +$SUMJINT$.% which has the failure modes from collecting its symptoms. We now state: -$$ fm(SUMJ) = \{ V_{in} DOM, V_{fb} DOM \} .$$ +$$ fm(SUMJUINT) = \{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$ -\subsubsection{Buffered Integrator} +% \subsubsection{Buffered Integrator} +% +% Following the signal path, the next functional group is the integrator. +% % +% This integrator is formed by placing $C1$ in the negative feedback loop of $IC2$\cite{aoe}[p.222]. +% The output of the integrator is fed into IC2, which acts as a buffer, +% %performing the function of +% isolating the integrator from any load on its output. +% These three components work together to form a buffered integrator, +% and nicely form a {\fg}. +% +% $$G^0_2 = \{IC1, C1, IC2\}.$$ +% +% The buffered integrator is analysed in table~\ref{tbl:intg}. +% +% +% \begin{table}[h+] +% \center +% \caption{IC1,C1,IC2 Buffered Integrator: Failure Mode Effects Analysis} % title of Table +% \label{tbl:intg} +% +% \begin{tabular}{|| l | l | c | c | l ||} \hline +% \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ +% & & & & \\ +% \hline \hline +% +% +% +% From the analysis in table~\ref{tbl:intg}, we can now create a derived component +% $BFINT$ which has the failure modes from collecting symptoms from the analysis in table~\ref{tbl:intg}. +% We can state +% +% $$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ +% -Following the signal path, the next functional group is the integrator. -% -This integrator is formed by placing $C1$ in the negative feedback loop of $IC2$\cite{aoe}[p.222]. -The output of the integrator is fed into IC2, which acts as a buffer, -%performing the function of -isolating the integrator from any load on its output. -These three components work together to form a buffered integrator, -and nicely form a {\fg}. -$$G^0_2 = \{IC1, C1, IC2\}.$$ - -The buffered integrator is analysed in table~\ref{tbl:intg}. +\subsubsection{High Impedance Signal Buffer (HISB)} +Next in the signal path (see figure~\ref{fig:sigmadeltablock}) is a signal buffer. +This presents a high impedance to the circuit driving it. +This prevents electrical loading, and thus interference with, the SUMJINT stage. +This is simply an op-amp +with the input connected to the +ve input and the -ve input grounded. +It therefore has the failure modes of an Op-amp. \begin{table}[h+] \center -\caption{IC1,C1,IC2 Buffered Integrator: Failure Mode Effects Analysis} % title of Table -\label{tbl:intg} + +% \center +\caption{ High Impedance Signal Buffer (HISB) : Failure Mode Effects Analysis} % title of Table \begin{tabular}{|| l | l | c | c | l ||} \hline - \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + + \textbf{Failure Scenario} & & \textbf{failure result} & & \textbf{Symptom} \\ & & & & \\ - \hline \hline - FS1: $IC1$ $HIGH$ & & output perm. high & & HIGH \\ - FS2: $IC1$ $LOW$ & & output perm. low & & LOW \\ \hline - FS3: $IC1$ $NOOP$ & & no current to drive C1 & & NO\_INTEGRATION \\ - FS4: $IC1$ $LOW\_SLEW$ & & signal delay to C1 & & NO\_INTEGRATION \\ \hline + \hline\hline + + FS5: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ + FS6: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline + FS7: $IC2$ $NOOP$ & & no current to output & & $NOOP$ \\ + FS8: $IC2$ $LOW\_SLEW$ & & delay signal & & $LOW\_SLEW$ \\ \hline - FS3: $C1$ $OPEN$ & & no capacitance & & NO\_INTEGRATION \\ - FS4: $C1$ $SHORT$ & & no capacitance & & NO\_INTEGRATION \\ \hline - -\hline - FS1: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ - FS2: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline - FS3: $IC2$ $NOOP$ & & no current drive & & LOW \\ - FS4: $IC2$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline -\hline + +% FS1: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ +% FS2: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline +% FS3: $IC2$ $NOOP$ & & no current drive & & LOW \\ +% FS4: $IC2$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline +% \hline \end{tabular} \end{table} - - -From the analysis in table~\ref{tbl:intg}, we can now create a derived component -$BFINT$ which has the failure modes from collecting symptoms from the analysis in table~\ref{tbl:intg}. -We can state - -$$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ - - - - - +% \hline +% +% \end{tabular} +% \end{table} \subsubsection{Digital level to analogue level conversion ($DL2AL$).} Digital level to analogue level conversion is performed by IC3 in conjunction with a potential divider formed by R3,R4. @@ -2113,19 +2159,41 @@ $$ fm (DL2AL^2) = \{ LOW, HIGH, LOW\_SLEW \} $$ \subsection{First {\fgs} analysed} -We have analysed the initial {\fgs} and can now take stock of the situation -and see what is now required. Figure~\ref{fig:sigdel1} shows how far the -hierarchy has been built. +We have analysed the initial {\fgs} and +have created our first {\dcs}. %and can now take stock of the situation +%and see what is now required. +%Figure~\ref{fig:sigdel1} shows which {\fgs} we have analysed so far. +%hierarchy has been built. +These are: +\begin{itemize} + \item SUMJINT --- A summing junction and integrator, + \item HISB --- A High impedance buffer, + \item DIGITALBUFF --- A one bit digital buffer, + \item DL2AL --- A digital to analog level converter. +\end{itemize} +These {\dcs} follow to signal path shown in figure~\ref{fig:sigmadeltablock}. +We now use these {\dcs} to create a final {\fg} to represent the failure mode +behaviour of the $\Sigma \Delta ADC$. We represent this +in the Euler diagram in figure~\ref{fig:eulersd}. -\begin{figure}[h+] +\begin{figure}[h] \centering - \includegraphics[width=400pt]{./CH5_Examples/sigdel1.png} - % sigdel1.png: 766x618 pixel, 72dpi, 27.02x21.80 cm, bb=0 0 766 618 - \caption{First stage of FMMD analysis: Sigma delta Converter} - \label{fig:sigdel1} + \includegraphics[width=400pt]{./CH5_Examples/eulersd.png} + % eulersd.png: 1018x334 pixel, 72dpi, 35.91x11.78 cm, bb=0 0 1018 334 + \caption{Euler diagram showing the functional grouping used to model the $\Sigma \Delta ADC$} + \label{fig:eulersd} \end{figure} +% +% \begin{figure}[h+] +% \centering +% \includegraphics[width=400pt]{./CH5_Examples/sigdel1.png} +% % sigdel1.png: 766x618 pixel, 72dpi, 27.02x21.80 cm, bb=0 0 766 618 +% \caption{First stage of FMMD analysis: Sigma delta Converter} +% \label{fig:sigdel1} +% \end{figure} + IC4 is as yet unused, the signal path connects IC4 and DL2AL. These seem natural candidates for the next {\fg}. @@ -2137,7 +2205,7 @@ BFINT and SUMJ are adjacent in the signal path and these are chosen as a {\fg} a \subsubsection{{\fg} $BFINT^1$ and $SUMJ^1$} -We now form a {\fg} with the two derived components $BFINT^1$ and $SUMJ^1$. +We now form a {\fg} with the two derived components $BFINT^1$ and $SUMJINT^1$. This forms a buffered integrating summing junction which we analyse in table~\ref{tbl:BISJ}. $$ G^1_0 = \{ BFINT^1, SUMJ^1 \} $$ @@ -2188,7 +2256,7 @@ called $BISJ^2$. The functional group formed by $IC4$ and $DL2AL$ takes the flip flop clocked and buffered value, and outputs it at analogue voltage levels for the summing junction. -$ G^2_1 = \{ IC4^0, DL2AL^2 \} $ +$ G^2_1 = \{ IC4^0, DL2AL^2, CLOCK\} $ We analyse the buffered flip flop circuitry in table~\ref{tbl:FFB}. @@ -2208,8 +2276,9 @@ We analyse the buffered flip flop circuitry in table~\ref{tbl:FFB}. FS5: $DL2AL^2$ $HIGH$ & & output perm. low & & $OUTPUT STUCK$ \\ \hline FS6: $DL2AL^2$ $LOW\_SLEW$ & & no current drive & & $LOW\_SLEW$ \\ + FS7: $CLOCK^0$ $STOPPED$ & & output stuck & & $OUTPUT STUCK$ \\ +\hline \hline - \end{tabular} \end{table} @@ -2325,6 +2394,27 @@ We now show the final hierarchy in figure~\ref{fig:sdadc}. + + + + + + + + + + + + + + + + + + + + + \section{Applying FMMD to Software} \label{sec:elecsw} FMMD can be applied to software, and thus we can build complete failure models diff --git a/submission_thesis/CH5_Examples/sigma_delta_block.dia b/submission_thesis/CH5_Examples/sigma_delta_block.dia index e9b5116..dbd8992 100644 Binary files a/submission_thesis/CH5_Examples/sigma_delta_block.dia and b/submission_thesis/CH5_Examples/sigma_delta_block.dia differ