night night edit, but have not eaten yet (GEDDIT)
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@ -65,32 +65,32 @@ failure mode of the component or sub-system}}}
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\linespread{0.953}
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\begin{document}
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\begin{document}
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%\pagestyle{fancy}
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%\pagestyle{fancy}
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@ -144,13 +144,16 @@ failure mode of the component or sub-system}}}
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This paper presents a worked example of FMEA applied to an
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This paper presents a worked example of FMEA applied to an
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integrated electronics/software system.
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integrated electronics/software system.
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%
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%
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FMEA methodologies trace from the 1940's and were designed to
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%FMEA methodologies trace from the 1940's and were designed to
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%model simple electro-mechanical systems.
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%
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FMEA methodologies were originally in the 1940's designed to
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model simple electro-mechanical systems.
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model simple electro-mechanical systems.
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%
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%
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Software generally sits on top of most modern safety critical control systems
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Software generally sits on top of most modern safety critical control systems
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and defines its most important system wide behaviour and communications.
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and defines its most important system wide behaviour and communications.
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%
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%
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Currently standards that demand FMEA for hardware(HFMEA) (e.g. EN298, EN61508),
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Currently standards that demand FMEA investigations for hardware(HFMEA) (e.g. EN298, EN61508),
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do not specify it for software, but instead specify good practise,
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do not specify it for software, but instead specify good practise,
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review processes and language feature constraints.
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review processes and language feature constraints.
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%
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%
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@ -161,12 +164,22 @@ traces component {\fms}
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to resultant system failures, software until recently, has been left in a non-analytical
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to resultant system failures, software until recently, has been left in a non-analytical
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limbo of best practises and constraints.
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limbo of best practises and constraints.
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Software FMEA has been proposed
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Software FMEA has been proposed
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in several forms. SFMEA is always performed separately from HFMEA.
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in several forms.
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%
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However, SFMEA is always performed separately from HFMEA.
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%
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%
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This paper seeks to examine the effectiveness of current and proposed SFMEA
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This paper seeks to examine the effectiveness of current and proposed SFMEA
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techniques, by using a analysing the chosen example, which is well known and understood
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techniques, by analysing a simple hybrid hardware/software system,
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from years of field experience, and determining how well the HFMEA and SFMEA
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which is in common use and has mature field experience. %
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analysis reports model the failure mode behaviour.
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%analysing the chosen example, which is well known and understood
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%
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Because the chosen example is well understood it is
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%, this example is
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useful
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to compare the results from these FMEA methodologies with
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the known failure mode behaviour.
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%from years of field experience, and determining how well the HFMEA and SFMEA
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%analysis reports model the failure mode behaviour.
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% %
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% %
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%If software and hardware integrated FMEA were possible, electro-mechanical-software hybrids could
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%If software and hardware integrated FMEA were possible, electro-mechanical-software hybrids could
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%be modelled, and so we could consider `complete' failure mode models.
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%be modelled, and so we could consider `complete' failure mode models.
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@ -205,7 +218,7 @@ component failure modes, %and by reasoning,
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tracing their effects through a system
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tracing their effects through a system
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and determining what system level failure modes could be caused.
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and determining what system level failure modes could be caused.
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%
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%
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FMEA dates from the 1940s where simple electro-mechanical systems were the norm.
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FMEA has its roots in the previous century where simple electro-mechanical systems were the norm.
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Modern control systems nearly always have a significant software/firmware element,
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Modern control systems nearly always have a significant software/firmware element,
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and not being able to model software with current FMEA methodologies
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and not being able to model software with current FMEA methodologies
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is a cause for criticism~\cite{safeware}[Ch.12].
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is a cause for criticism~\cite{safeware}[Ch.12].
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@ -260,19 +273,20 @@ base component {\fms}, and translating them into system level events/failures~\c
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In a complicated system, mapping a component failure mode to a system level failure
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In a complicated system, mapping a component failure mode to a system level failure
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will mean a long reasoning distance; that is to say the actions of the
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will mean a long reasoning distance; that is to say the actions of the
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failed component will have to be traced through
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failed component will have to be traced through
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several sub-systems, gauging its effects with other components.
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several sub-systems, gauging its effects with and on other components.
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%
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%
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With software at the higher levels of these sub-systems,
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With software at the higher levels of these sub-systems,
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we have yet another layer of complication.
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we have yet another layer of complication.
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%
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%
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In order to integrate software, %in a meaningful way
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%In order to integrate software, %in a meaningful way
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we need to re-think the
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%we need to re-think the
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FMEA concept of simply mapping a base component failure to a system level event.
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%FMEA concept of simply mapping a base component failure to a system level event.
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%
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%
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SFMEA regards the components to be the variables used by the programs.
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SFMEA regard, in place of hardware components, the variables used by the programs to be their equivalent~\cite{procsfmea}.
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These variables could become erroneously over-written,
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The failure modes of these variables, are that they could become erroneously over-written,
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by calculated incorrectly (due to a mistake by the programmer, or a fault in the micro-processor it is running on, or
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calculated incorrectly (due to a mistake by the programmer, or a fault in the micro-processor it is running on), or
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by radiation causing bits to be erroneously altered.
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external influences such as
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ionising radiation causing bits to be erroneously altered.
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\paragraph{A more-complete Failure Mode Model}
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\paragraph{A more-complete Failure Mode Model}
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@ -287,8 +301,8 @@ by radiation causing bits to be erroneously altered.
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%
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%
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In order to obtain a more complete failure mode model of
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In order to obtain a more complete failure mode model of
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a hybrid electronic/software system we need to analyse
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a hybrid electronic/software system we need to analyse
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the hardware, the software, the hardware the software runs on,
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the hardware, the software, the hardware the software runs on (i.e. the software's medium),
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and the software hardware interface.
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and the software/hardware interface.
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%
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%
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HFMEA is a well established technique and needs no further description in this paper.
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HFMEA is a well established technique and needs no further description in this paper.
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@ -301,7 +315,7 @@ to supply a current signal to represent the value to be sent~\cite{aoe}[p.934].
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Usually, $4mA$ represents a zero or starting value and $20mA$ represents the full scale,
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Usually, $4mA$ represents a zero or starting value and $20mA$ represents the full scale,
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and this is referred to as {\ft} signalling.
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and this is referred to as {\ft} signalling.
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%
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%
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{\ft} has an electrical advantage as well because the current in a loop is constant~\cite{aoe}[p.20].
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{\ft} has an electrical advantage as well because the current in an electronic loop is constant~\cite{aoe}[p.20].
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Thus resistance in the wires between the source and the receiving end is not an issue
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Thus resistance in the wires between the source and the receiving end is not an issue
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that can alter the accuracy of the signal.
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that can alter the accuracy of the signal.
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%
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%
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@ -332,25 +346,26 @@ The diagram in figure~\ref{fig:ftcontext} shows some equipment which is sending
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signal to a micro-controller system.
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signal to a micro-controller system.
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The signal is locally driven over a load resistor, and then read into the micro-controller via
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The signal is locally driven over a load resistor, and then read into the micro-controller via
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an ADC and its multiplexer.
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an ADC and its multiplexer.
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With the voltage detected at the ADC the multiplexer can read the intended quantitative
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With the voltage detected at the ADC the multiplexer we read the intended quantitative
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value from the external equipment.
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value from the external equipment.
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\subsection{Simple Software Example}
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\subsection{Simple Software Example}
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Consider a software function that reads a {\ft} input, and returns a value between 0 and 999 (i.e. per mil $\permil$)
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Consider a software function that reads a {\ft} input, and returns a value between 0 and 999 (i.e. per mil $\permil$)
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representing the current detected with an additional error indication flag.
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representing the value intended by the current detected, with an additional error indication flag to indicate the validity
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of the value returned.
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%
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%
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Let us assume the {\ft} detection is via a \ohms{220} resistor, and that we read a voltage
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Let us assume the {\ft} detection is via a \ohms{220} resistor, and that we read a voltage
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from an ADC into the software.
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from an ADC into the software.
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Let us define any value outside the 4mA to 20mA range as an error condition.
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Let us define any value outside the 4mA to 20mA range as an error condition.
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%
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%
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As a voltage, we use ohms law~\cite{aoe} to determine the voltage ranges: $V=IR$, $0.004A * \ohms{220} = 0.88V$
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As a voltage, we use ohms law~\cite{aoe} to determine the voltage ranges: $V=IR$, $0.004A * \ohms{220} = 0.88V$
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and $0.020A * \ohms{220} = 4.4V$.
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and $$0.020A * \ohms{220} = 4.4V \;.$$
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%
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%
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Our acceptable voltage range is therefore
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Our acceptable voltage range is therefore
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%
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%
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$(V \ge 0.88) \wedge (V \le 4.4) \; .$
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$$(V \ge 0.88) \wedge (V \le 4.4) \; .$$
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This voltage range forms our input requirement.
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This voltage range forms our input requirement.
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%
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%
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@ -479,7 +494,7 @@ calls {\em read\_ADC}, which in turn interacts with the hardware/electronics.
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This software is above the hardware in the conceptual call tree---from a programmatic perspective---%in software terms---the
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This software is above the hardware in the conceptual call tree---from a programmatic perspective---%in software terms---the
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software is reading values from the `lower~level' electronics.
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software is reading values from the `lower~level' electronics.
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%
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%
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FMEA is always a bottom-up process and so we must begin with this hardware.
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%FMEA is always a bottom-up process and so we must begin with this hardware.
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%
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%
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The hardware is simply a load resistor, connected across an ADC input
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The hardware is simply a load resistor, connected across an ADC input
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pin on the micro-controller and ground.
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pin on the micro-controller and ground.
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@ -504,8 +519,8 @@ the multiplexer and the analogue to digital converter.
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\label{tbl:r420i}
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\label{tbl:r420i}
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\begin{tabular}{|| l | c | l ||} \hline
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\begin{tabular}{|| l | c | l ||} \hline
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\textbf{Failure} & \textbf{failure} & \textbf{System Failure} \\
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\textbf{Failure} & \textbf{failure} & \textbf{System} \\
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\textbf{Scenario} & \textbf{effect} & \\ \hline
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\textbf{Scenario} & \textbf{effect} & \textbf{Failure} \\ \hline
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\hline
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\hline
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$R$ & OPEN~\cite{en298}[Ann.A] & $LOW$ \\
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$R$ & OPEN~\cite{en298}[Ann.A] & $LOW$ \\
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& & $READING$ \\ \hline
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& & $READING$ \\ \hline
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@ -537,7 +552,7 @@ For software FMEA we take the variables used by the system,
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and examine what could happen if they are corrupted in various ways~\cite{procsfmea, embedsfmea}.
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and examine what could happen if they are corrupted in various ways~\cite{procsfmea, embedsfmea}.
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From the function $read\_4\_20\_input()$ we have the variables $error\_flag$,
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From the function $read\_4\_20\_input()$ we have the variables $error\_flag$,
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$input\_volts$ and $value$: from the function $read\_ADC()$, $timeout$, $ADCMUX$, $ADCGO$, $dval$.
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$input\_volts$ and $value$: from the function $read\_ADC()$, $timeout$, $ADCMUX$, $ADCGO$, $dval$.
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We must now determine putative system failure modes for these variables becoming corrupted.
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We must now determine putative system failure modes for these variables becoming corrupted, this is performed in table~\ref{tbl:sfmea}.
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{
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{
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@ -547,8 +562,8 @@ We must now determine putative system failure modes for these variables becoming
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\label{tbl:sfmea}
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\label{tbl:sfmea}
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\begin{tabular}{|| l | c | l ||} \hline
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\begin{tabular}{|| l | c | l ||} \hline
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\textbf{Failure} & \textbf{failure} & \textbf{System Failure} \\
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\textbf{Failure} & \textbf{failure} & \textbf{System} \\
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\textbf{Scenario} & \textbf{effect} & \\ \hline
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\textbf{Scenario} & \textbf{effect} & \textbf{Failure} \\ \hline
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\hline
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\hline
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$error\_flag$ & set FALSE & $VAL\_ERROR$ \\
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$error\_flag$ & set FALSE & $VAL\_ERROR$ \\
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& & \\ \hline
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& & \\ \hline
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@ -592,7 +607,7 @@ We must now determine putative system failure modes for these variables becoming
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Microprocessors/Microcontrollers have sets of known failure modes, these include RAM, ROM
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Microprocessors/Microcontrollers have sets of known failure modes, these include RAM, ROM
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EEPROM failure\footnote{EEPROM failure is not applicable for this example.} and
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EEPROM failure\footnote{EEPROM failure is not applicable for this example.} and
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oscillator clock timing~\cite{sfmeaauto}.
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oscillator clock timing
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@ -603,11 +618,11 @@ oscillator clock timing~\cite{sfmeaauto}.
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\label{tbl:sfmeaup}
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\label{tbl:sfmeaup}
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\begin{tabular}{|| l | c | l ||} \hline
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\begin{tabular}{|| l | c | l ||} \hline
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\textbf{Failure} & \textbf{failure} & \textbf{System Failure} \\
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\textbf{Failure} & \textbf{failure} & \textbf{System} \\
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\textbf{Scenario} & \textbf{effect} & \\ \hline
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\textbf{Scenario} & \textbf{effect} & \textbf{Failure} \\ \hline
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\hline
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\hline
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$RAM$ & variable corruption & All errors \\
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$RAM$ & variable & All errors \\
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& & from table~\ref{tbl:sfmea} \\ \hline
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& corruption & from table~\ref{tbl:sfmea} \\ \hline
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$RAM$ & program flow & process \\
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$RAM$ & program flow & process \\
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& & halts / crashes \\ \hline
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& & halts / crashes \\ \hline
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@ -632,51 +647,93 @@ oscillator clock timing~\cite{sfmeaauto}.
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\end{table}
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\end{table}
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}
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}
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\clearpage
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\section{Software FMEA - The software hardware interface}
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\section{Software FMEA - The software/hardware interface}
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As FMEA is applied separately to software and hardware
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As FMEA is applied separately to software and hardware
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the interface between them is an undefined factor.
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the interface between them is an undefined factor.
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Ozarin~\cite{sfmeainterface} recommends that an FMEA report be written
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Ozarin~\cite{sfmeainterface,procsfmea} recommends that an FMEA report be written
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to focus on the software/hardware interface.
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to focus on the software/hardware interface.
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The software/hardware interface has
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specific problems common to many systems and configurations
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and these are described in~\cite{sfmeainterface}.
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%An interface FMEA is performed in table~\ref{hwswinterface}.
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%
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The hardware to software interface for the {\ft} example is handled
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The hardware to software interface for the {\ft} example is handled
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by the 'C' function $read\_ADC()$.
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by the 'C' function $read\_ADC()$.
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~\cite{sfmeaauto}.
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%
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% An FMEA of the `software~medium' is given in table~\ref{tbl:sfmeaup}.
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\paragraph{Timing and Synchronisation.}
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The $ADCOUT$ register, where the raw ADC value is read
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is an internal register used by the ADC and presented
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as a readable memory location when the ADC
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has finished updating it.
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Reading it at the wrong time would
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cause an invalid value to be read.
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The synchronisation is performed by polling an $ADCGO$
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bit, a flag mapped to memory by which the ADC indicates that the data is ready.
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\paragraph{Interrupt Contention.}
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Were an interrupt to also attempt to read from the ADC
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the ADCMUX could be altered, causing the non-interrupt
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routine to read from the wrong channel.
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\paragraph{Data Formatting.}
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The ADC may use a big-endian or little endian integer
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format. It may also right or left justify the bits in its value.
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\section{Conclusion}
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\section{Conclusion}
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%
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%
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The FMMD method has been demonstrated using an the industry standard {\ft}
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This paper has picked a very simple example (the industry standard {\ft}
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input circuit and software.
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input circuit and software) to demonstrate
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SFMEA and HFMEA methodologies used to describe a failure mode model.
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%Even a modest system would be far too large to analyse in conference paper
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%and this
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%
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%
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The {\dc} representing the {\ft} reader
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%The {\dc} representing the {\ft} reader
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shows that by taking a
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%shows that by taking a
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%modular approach for FMEA, i.e. FMMD, we can integrate
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%modular approach for FMEA, i.e. FMMD, we can integrate
|
||||||
four FMEA reports we can model the failure mode behaviour from
|
Our model is described by four FMEA reports; and these % we can model the failure mode behaviour from
|
||||||
several perspectives, for
|
model the system from four several perspectives.
|
||||||
software and electrical systems% models.
|
|
||||||
%
|
|
||||||
With this analysis
|
|
||||||
we have stages along the `reasoning~path' linking the failure modes from the
|
|
||||||
electronics to those in the software.
|
|
||||||
Each {\fg} to {\dc} transition represents a
|
|
||||||
reasoning stage.
|
|
||||||
%
|
|
||||||
%
|
%
|
||||||
With traditional FMEA methods the reasoning~distance is large, because
|
With traditional FMEA methods the reasoning~distance is large, because
|
||||||
it stretches from the component failure mode to the top---or---system level failure.
|
it stretches from the component failure mode to the top---or---system level failure.
|
||||||
|
%
|
||||||
|
With these four analysis reports
|
||||||
|
we do not have stages along the `reasoning~path' linking the failure modes from the
|
||||||
|
electronics to those in the software.
|
||||||
|
%Software is often written `defensively' but t
|
||||||
|
%Each {\fg} to {\dc} transition represents a
|
||||||
|
%reasoning stage.
|
||||||
|
%
|
||||||
|
%
|
||||||
%For this reason applying traditional FMEA to software stretches
|
%For this reason applying traditional FMEA to software stretches
|
||||||
%the reasoning distance even further.
|
%the reasoning distance even further.
|
||||||
%
|
%
|
||||||
In fact these reasoning paths overlap ---or even by-pass one another---
|
In fact many these reasoning paths overlap---or even by-pass one another---
|
||||||
it is very difficult to gauge cause and effect. For instance
|
it is very difficult to gauge cause and effect.
|
||||||
were the ADC to have a small value error, say adding
|
For instance, hardware failures are not analysed in the context of how they will
|
||||||
a small percentage onto the value, we would be unable to
|
be handled (or missed) by the software.
|
||||||
detect this under the analysis conditions for this model, or
|
%
|
||||||
be able to pinpoint it.
|
System outputs commanded from may not take into account particular
|
||||||
|
hardware limitations etc.
|
||||||
|
|
||||||
|
The interface FMEA does serve to provide a useful
|
||||||
|
checklist to ensure conventions used by the hardware
|
||||||
|
and software are not mismatched.
|
||||||
|
|
||||||
|
However, while these techniques ensure that the software and hardware is
|
||||||
|
viewed and analysed from several perspectives, it cannot be termed a homogeneous
|
||||||
|
failure mode model.
|
||||||
|
% For instance
|
||||||
|
% were the ADC to have a small value error, say adding
|
||||||
|
% a small percentage onto the value, we would be unable to
|
||||||
|
% detect this under the analysis conditions for this model, or
|
||||||
|
% be able to pinpoint it.
|
||||||
|
%
|
||||||
|
|
||||||
|
|
||||||
{
|
{
|
||||||
|
Loading…
Reference in New Issue
Block a user