From b9d80c11d1f0fff8aaf64bac4fc9460271ee838a Mon Sep 17 00:00:00 2001 From: "Robin P. Clark" Date: Thu, 11 Oct 2012 14:05:35 +0100 Subject: [PATCH] luchtime edit (geddit) --- submission_thesis/CH5_Examples/copy.tex | 293 +++++++++++++----------- submission_thesis/style.tex | 4 +- 2 files changed, 158 insertions(+), 139 deletions(-) diff --git a/submission_thesis/CH5_Examples/copy.tex b/submission_thesis/CH5_Examples/copy.tex index 926b143..68cd068 100644 --- a/submission_thesis/CH5_Examples/copy.tex +++ b/submission_thesis/CH5_Examples/copy.tex @@ -29,7 +29,7 @@ a variety of typical embedded system components including analogue/digital and e The first section ~\ref{sec:determine_fms} looks at how we determine failure mode sets for {\bcs} (in the context of the safety standards -we are conforming to for our particular project). +we are using for our particular project). % This is followed by several example FMMD analyses, the first analysing a common configuration of @@ -50,13 +50,13 @@ where its re-use is appropriate in the first stage and not in the second. % Section~\ref{sec:fivepolelp} analyses a Sallen-Key based five pole low pass filter. -This demonstrates FMMD being able to re-use the first Sallen-Key encountered as a {\dc}, thus -saving time and effort for the analyst. +This demonstrates FMMD being able to re-use the first Sallen-Key analysis, %encountered as a {\dc} +thus saving time and effort for the analyst. % Section~\ref{sec:bubba} shows FMMD applied to a circular circuit topology---the `Bubba' oscillator---which uses four op-amp stages with supporting components. % -Section~\ref{sec:sigmadelta} shows FMMD analysing the sigma delta analogue to digital converter---which operates on both +Section~\ref{sec:sigmadelta} shows FMMD analysing the sigma delta analogue to digital converter---again with a circular signal path---but which also operates on both analogue and digital signals. % % Moving Pt100 to metrics @@ -293,7 +293,7 @@ $$ fm(R) = \{ OPEN, SHORT \} . $$ \centering \includegraphics[width=200pt]{CH5_Examples/lm258pinout.jpg} % lm258pinout.jpg: 478x348 pixel, 96dpi, 12.65x9.21 cm, bb=0 0 359 261 - \caption{Pinout for an LM358 dual OP-AMP} + \caption{Pinout for an LM358 dual OpAmp} \label{fig:lm258} \end{figure} @@ -305,10 +305,10 @@ For the purpose of example, we look at a typical op-amp designed for instrumentation and measurement, the dual packaged version of the LM358~\cite{lm358} (see figure~\ref{fig:lm258}), and use this to compare the failure mode derivations from FMD-91 and EN298. -\paragraph{ Failure Modes of an OP-AMP according to FMD-91 } +\paragraph{ Failure Modes of an OpAmp according to FMD-91 } %Literature suggests, latch up, latch down and oscillation. -For OP-AMP failures modes, FMD-91\cite{fmd91}{3-116] states, +For OpAmp failures modes, FMD-91\cite{fmd91}{3-116] states, \begin{itemize} \item Degraded Output 50\% Low Slew rate - poor die attach \item No Operation - overstress 31.3\% @@ -318,11 +318,11 @@ For OP-AMP failures modes, FMD-91\cite{fmd91}{3-116] states, Again these are mostly internal causes of failure, more of interest to the component manufacturer than a designer looking for the symptoms of failure. -We need to translate these failure causes within the OP-AMP into {\fms}. +We need to translate these failure causes within the OpAmp into {\fms}. We can look at each failure cause in turn, and map it to potential {\fms} suitable for use in FMEA investigations. -\paragraph{OP-AMP failure cause: Poor Die attach} +\paragraph{OpAmp failure cause: Poor Die attach} The symptom for this is given as a low slew rate. This means that the op-amp will not react quickly to changes on its input terminals. This is a failure symptom that may not be of concern in a slow responding system like an @@ -343,18 +343,18 @@ We map this failure cause to $HIGH$ or $LOW$. \paragraph{Open $V_+$} This failure cause will mean that the minus input will have the very high gain -of the OP-AMP applied to it, and the output will be forced HIGH or LOW. +of the OpAmp applied to it, and the output will be forced HIGH or LOW. We map this failure cause to $HIGH$ or $LOW$. -\paragraph{Collecting OP-AMP failure modes from FMD-91} -We can define an OP-AMP, under FMD-91 definitions to have the following {\fms}. +\paragraph{Collecting OpAmp failure modes from FMD-91} +We can define an OpAmp, under FMD-91 definitions to have the following {\fms}. \begin{equation} \label{eqn:opampfms} - fm(OP-AMP) = \{ HIGH, LOW, NOOP, LOW_{slew} \} + fm(OpAmp) = \{ HIGH, LOW, NOOP, LOW_{slew} \} \end{equation} -\paragraph{Failure Modes of an OP-AMP according to EN298} +\paragraph{Failure Modes of an OpAmp according to EN298} EN298 does not specifically define OP\_AMPS failure modes; these can be determined by following a procedure for `integrated~circuits' outlined in @@ -434,7 +434,7 @@ that we got from FMD-91, listed in equation~\ref{eqn:opampfms}. %\clearpage -\subsubsection{Failure modes of an OP-AMP} +\subsubsection{Failure modes of an OpAmp} \label{sec:opamp_fms} For the purpose of the examples to follow, the op-amp will @@ -450,7 +450,7 @@ The EN298 pinouts failure mode technique cannot reveal failure modes due to inte The FMD-91 entries for op-amps are not directly usable as component {\fms} in FMEA or FMMD and require interpretation. -%For our OP-AMP example could have come up with different symptoms for both sides. Cannot predict the effect of internal errors, for instance ($LOW_{slew}$) +%For our OpAmp example could have come up with different symptoms for both sides. Cannot predict the effect of internal errors, for instance ($LOW_{slew}$) %is missing from the EN298 failure modes set. @@ -661,7 +661,7 @@ If we consider the input will only be positive, we can invert the potential divi We can form a {\dc} from this, and call it an inverted potential divider $INVPD$. -We can now form a {\fg} from the OP-AMP and the $INVPD$ +We can now form a {\fg} from the OpAmp and the $INVPD$ \begin{table}[h+] \caption{Inverting Amplifier: Single failure analysis} @@ -792,7 +792,7 @@ We can now form a {\fg} from the OP-AMP and the $INVPD$ $$ fm(INVAMP) = \{ {lowpass}, {high}, {low} \}.$$ -\subsection{Second Approach: Inverting OP-AMP analysing with three components in one larger {\fg}} +\subsection{Second Approach: Inverting OpAmp analysing with three components in one larger {\fg}} Here we analyse the same problem without using an intermediate $PD$ derived component. @@ -1275,7 +1275,7 @@ The op-amp IC1 is being used simply as a buffer. By placing it between the next on the signal path, we remove the possibility of unwanted signal feedback. The buffer is one of the simplest op-amp configurations. It has no other components, and so we can now form a {\fg} -from the $FirstOrderLP$ and the OP-AMP component. +from the $FirstOrderLP$ and the OpAmp component. \begin{table}[ht] \caption{First Stage LP1: Failure Mode Effects Analysis: Single Faults} % title of Table @@ -1937,7 +1937,7 @@ there are more {\dcs} and this increases the possibility of re-use. -\section{Sigma Delta Analogue to Digital Converter ($\Sigma \Delta ADC$).} %($\Sigma \Delta ADC$)} +\section{Sigma Delta Analogue to Digital Converter (\sd).} %($\Sigma \Delta ADC$)} \label{sec:sigmadelta} The following example is used to demonstrate FMMD analysis of a mixed analogue and digital circuit (see figure~\ref{fig:sigmadelta}). \begin{figure}[h] @@ -1956,7 +1956,7 @@ The following example is used to demonstrate FMMD analysis of a mixed analogue a \centering \includegraphics[width=200pt,keepaspectratio=true]{./CH5_Examples/sigma_delta_block.png} % sigma_delta_block.png: 828x367 pixel, 72dpi, 29.21x12.95 cm, bb=0 0 828 367 - \caption{Electrical signal path Block diagram: $\Sigma \Delta ADC$} % Analogue to Digital Converter } + \caption{Electrical signal path Block diagram: \sd} % Analogue to Digital Converter } \label{fig:sigmadeltablock} \end{figure} @@ -1986,11 +1986,14 @@ and fed into the summing integrator completing the negative feedback loop. \subsection{FMMD analysis of \sd } -The partslist for the \sd : +%The partslist for the \sd : % -$$\{ IC1, IC2, IC3, IC4, R1, R2, R3, R4, C1 \} $$. +%$$\{ IC1, IC2, IC3, IC4, R1, R2, R3, R4, C1 \} $$. % -IC1,2 and 3 are all Op-amps and we have failure modes from section~\ref{sec:opampfm}. +The parts for the \sd are a mixture of analogue (resistors, capacitors, OpAmps) and digital +(D type flip flop, and a digital clock). We examine the failure modes of all components in this circuit below. +% +IC1,2 and 3 are all OpAmps and we have failure modes from section~\ref{sec:opamp_fms}. % $$ fm(OPAMP) = \{ HIGH, LOW, NOOP, LOW\_SLEW \} $$ % @@ -2013,7 +2016,8 @@ $$ fm ( CLOCK ) = \{ STOPPED \} $$ \subsection{Identifying initial {\fgs}} \subsubsection{Summing Junction Integrator (SUMJINT)} -We now need to choose {\fgs}. The signal path is circular, but we can start +We now need to choose {\fgs}. The most obvious way to find initial {\fgs} id +to follow the signal path. The signal path is circular, but we can start with the input voltage, which is applied via $R2$, we term this voltage $V_{in}$. % The feedback voltage for the ADC is supplied via $R1$, we term this voltage as $V_{fb}$. @@ -2024,12 +2028,12 @@ This can be our first {\fg} and we analyse it in table~\ref{tbl:sumjint}. %For the symptoms, we have to think in terms of the effect %on its performance as a summing junction and not be %distracted by the integrator formed by $C_1$ and $IC1$. - -$$G^0_1 = \{R1, R2 \}$$ +% +$$FG = \{R1, R2, IC1, C1 \}$$ \begin{table}[h+] \center -\caption{ Summing Junction Integrator($SUMJINT$): Failure Mode Effects Analysis} % title of Table +\caption{Summing Junction Integrator($SUMJINT$): Failure Mode Effects Analysis} % title of Table \label{tbl:sumjint} \begin{tabular}{|| l | l | c | c | l ||} \hline @@ -2067,48 +2071,16 @@ $$G^0_1 = \{R1, R2 \}$$ % \end{table} -From the analysis in table~\ref{tbl:sumj} we collect symptoms. -We can create the derived component -$SUMJINT$.% which has the failure modes from collecting its symptoms. +From the analysis in table~\ref{tbl:sumjint} we collect symptoms. +We create the derived component +$SUMJINT$ and assign it the failure modes collected above.% which has the failure modes from collecting its symptoms. We now state: -$$ fm(SUMJUINT) = \{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$ +$$ fm(SUMJUINT^1_0) = \{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$ -% \subsubsection{Buffered Integrator} -% -% Following the signal path, the next functional group is the integrator. -% % -% This integrator is formed by placing $C1$ in the negative feedback loop of $IC2$\cite{aoe}[p.222]. -% The output of the integrator is fed into IC2, which acts as a buffer, -% %performing the function of -% isolating the integrator from any load on its output. -% These three components work together to form a buffered integrator, -% and nicely form a {\fg}. -% -% $$G^0_2 = \{IC1, C1, IC2\}.$$ -% -% The buffered integrator is analysed in table~\ref{tbl:intg}. -% -% -% \begin{table}[h+] -% \center -% \caption{IC1,C1,IC2 Buffered Integrator: Failure Mode Effects Analysis} % title of Table -% \label{tbl:intg} -% -% \begin{tabular}{|| l | l | c | c | l ||} \hline -% \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ -% & & & & \\ -% \hline \hline -% -% -% -% From the analysis in table~\ref{tbl:intg}, we can now create a derived component -% $BFINT$ which has the failure modes from collecting symptoms from the analysis in table~\ref{tbl:intg}. -% We can state -% -% $$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ -% +That is the failure modes of our new {\dc} $SUMJINT^1_0$ are $\{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$ +\clearpage \subsubsection{High Impedance Signal Buffer (HISB)} @@ -2123,7 +2095,11 @@ It therefore has the failure modes of an Op-amp. \center % \center -\caption{ High Impedance Signal Buffer (HISB) : Failure Mode Effects Analysis} % title of Table +\caption{ High Impedance Signal Buffer : Failure Mode Effects Analysis} % title of Table + +This is an OpAmp in a signal buffer configuration. +As it is performing one particular function +we my consider it as a derived component, that of a High Impedance Signal Buffer (HISB). \begin{tabular}{|| l | l | c | c | l ||} \hline @@ -2134,24 +2110,19 @@ It therefore has the failure modes of an Op-amp. \hline\hline - FS5: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ - FS6: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline - FS7: $IC2$ $NOOP$ & & no current to output & & $NOOP$ \\ - FS8: $IC2$ $LOW\_SLEW$ & & delay signal & & $LOW\_SLEW$ \\ \hline + FS1: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ + FS2: $IC2$ $LOW$ & & output perm. low & & LOW \\ + FS3: $IC2$ $NOOP$ & & no current to output & & $NOOP$ \\ + FS4: $IC2$ $LOW\_SLEW$ & & delay signal & & $LOW\_{SLEW}$ \\ \hline -% FS1: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ -% FS2: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline -% FS3: $IC2$ $NOOP$ & & no current drive & & LOW \\ -% FS4: $IC2$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline -% \hline - \end{tabular} \end{table} % \hline % % \end{tabular} % \end{table} +We create the {\dc} $HISB^1_1$ and it failure mode may be stated as $fm(HISB^1_1) = \{HIGH, LOW, NOOP, LOW_{SLEW} \}$. \subsubsection{Digital level to analogue level conversion ($DL2AL$).} Digital level to analogue level conversion is performed by IC3 in conjunction with a potential divider formed by R3,R4. @@ -2161,27 +2132,27 @@ to the inverting input of IC3. \paragraph{Potential divider Formed by R3,R4.} We re-use the analysis from table~\ref{tbl:pdfmea}, and use the derived component $PD$ to represent the potential divider formed by R3 and R4. Because PD is a derived component, we can denote this -by super-scripting it with its abstraction level of 1, thus $PD^1$. +by super-scripting it with its abstraction level of 1, thus $PD$. $$ -fm(PD^1) = \{ HIGH, LOW \}. +fm(PD) = \{ HIGH, LOW \}. $$ - +% IC3 is an op-amp and has the failure modes $$fm(IC3) = \{\{ HIGH, LOW, NOOP, LOW\_SLEW \} . $$ - +% The digital signal is supplied to the non-inverting input. The output is a voltage level in the analogue domain $-V$ or $+V$. - -We now form a {\fg} from $PD^1$ and $IC3$. - -$$ G^1_0 = \{ PD^1, IC3 \} $$ - -We now analyse the {\fg} $G^1$ in table~\ref{tbl:DS2AS}. -%$$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ +% +We now form a {\fg} from $PD $ and $IC3$. +% +$$ FG = \{ PD , IC3 \} $$ +% +We now analyse the {\fg} $G $ in table~\ref{tbl:DS2AS}. + \begin{table}[h+] \center -\caption{$PD^1, IC3$ Digital level to analogue level converter: Failure Mode Effects Analysis} % title of Table +\caption{$PD , IC3$ Digital level to analogue level converter: Failure Mode Effects Analysis} % title of Table \label{tbl:DS2AS} \begin{tabular}{|| l | l | c | c | l ||} \hline @@ -2192,34 +2163,78 @@ We now analyse the {\fg} $G^1$ in table~\ref{tbl:DS2AS}. \textbf{cause} & & \textbf{Effect} & & \textbf{Failure Mode} \\ \hline \hline - FS1: $PD^1$ $HIGH$ & & output perm. low & & LOW \\ - FS2: $PD^1$ $LOW$ & & output perm. low & & HIGH \\ \hline + FS1: $PD $ $HIGH$ & & output perm. low & & LOW \\ + FS2: $PD $ $LOW$ & & output perm. low & & HIGH \\ \hline \hline FS3: $IC3$ $HIGH$ & & output perm. high & & HIGH \\ - FS4: $IC3$ $LOW$ & & output perm. low & & LOW \\ \hline + FS4: $IC3$ $LOW$ & & output perm. low & & LOW \\ FS5: $IC3$ $NOOP$ & & no current drive & & LOW \\ - FS6: $IC3$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline + FS6: $IC3$ $LOW\_{SLEW}$ & & delayed signal & & $LOW\_{SLEW}$ \\ \hline \hline \end{tabular} \end{table} -We collect the symptoms of failure $\{ LOW, HIGH, LOW\_SLEW \}$. +We collect the symptoms of failure $\{ LOW, HIGH, LOW\_{SLEW} \}$. We can now derive a new component to represent the level conversion and call it $DL2AL$. -$$ DL2AL^2 = D(G^1_0) $$ +$$ DL2AL = D(FG = \{ PD , IC3 \}) $$ -$$ fm (DL2AL^2) = \{ LOW, HIGH, LOW\_SLEW \} $$ +$$ fm (DL2AL^2) = \{ LOW, HIGH, LOW\_{SLEW} \} $$ + +\clearpage - - -% \subsubsection{digital clocked memory (flip-flop).} +\subsubsection{$DIGBUF$ --- digital clocked memory (flip-flop).} % % This is a single component as a {\fg}, and we can state % $$ fm (DCM) = \{ HIGH, LOW, NOOP \} $$ +The digital element of the {\sd}, is the one bit memory, or D type flip flop. This +buffers the feedback result and provides the output bit stream. +We create a {\fg} from the CLOCK and IC4 to model this digital buffer. + +$$FG = \{ IC4, CLOCK \}$$ + + +%% DIGBUF --- Digital Buffer + +We now analyse this {\fg} in table~\ref{tbl:digbuf}. + + +\begin{table}[h+] +\center +\caption{$ IC4, CLOCK $ Digital Buffer: Failure Mode Effects Analysis} % title of Table +\label{tbl:digbuf} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + %\textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + % & & & & \\ + % & & & & \\ +\textbf{Failure} & & \textbf{$DIGBUF$ } & & \textbf{Derived Component} \\ + \textbf{cause} & & \textbf{Effect} & & \textbf{Failure Mode} \\ + %$$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$ + \hline \hline + FS1: $CLOCK$ $STOPPED$ & & buffer stopped & & STOPPED \\ \hline + + FS2: $IC4$ $HIGH$ & & buffer stopped & & STOPPED \\ + FS3: $IC4$ $LOW$ & & buffer stopped & & STOPPED \\ + FS4: $IC4$ $NOOP$ & & no current drive & & LOW \\ \hline + \hline +\hline + +\end{tabular} +\end{table} + +We collect the symptoms of failure $\{ LOW, STOPPED \}$. +We can now derive a new component to represent the level conversion and call it $DIGBUF$. + + +$$ fm (DIGBUF) = \{ LOW, STOPPED \} $$ + + +%%% END DIGBUF \subsection{First {\fgs} analysed} @@ -2234,12 +2249,14 @@ These are: \item HISB --- A High impedance buffer, \item DIGITALBUFF --- A one bit digital buffer, \item DL2AL --- A digital to analog level converter. + \item DIGBUF --- A digital one bit buffer/memory \end{itemize} These {\dcs} follow to signal path shown in figure~\ref{fig:sigmadeltablock}. We now use these {\dcs} to create a final {\fg} to represent the failure mode behaviour of the $\Sigma \Delta ADC$. We represent this in the Euler diagram in figure~\ref{fig:eulersd}. - +The next stage is to create {\fgs} from these initial {\dcs} +and make a complete failure mode mode for the {\sd}. \begin{figure}[h] \centering @@ -2259,26 +2276,24 @@ in the Euler diagram in figure~\ref{fig:eulersd}. % \end{figure} -IC4 is as yet unused, the signal path connects IC4 and DL2AL. These seem natural candidates -for the next {\fg}. +%IC4 is as yet unused, the signal path connects IC4 and DL2AL. These seem natural candidates +%for the next {\fg}. BFINT and SUMJ are adjacent in the signal path and these are chosen as a {\fg} as well. \clearpage -\subsubsection{{\fg} $BFINT^1$ and $SUMJ^1$} +\subsubsection{{\fg} $HISB$ and $SUMJINT$} -We now form a {\fg} with the two derived components $BFINT^1$ and $SUMJINT^1$. +We now form a {\fg} with the two derived components $HISB$ and $SUMJINT$. This forms a buffered integrating summing junction which we analyse in table~\ref{tbl:BISJ}. -$$ G^1_0 = \{ BFINT^1, SUMJ^1 \} $$ - -%$$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ -%$$ fm(SUMJ) = \{ V_{in} DOM, V_{fb} DOM \} .$$ +$$ FG = \{ HISB, SUMJINT \} $$ + \begin{table}[h+] -\caption{ $BFINT^1, SUMJ^1$ buffered integrating summing junction($BISJ$): Failure Mode Effects Analysis} % title of Table +\caption{ $HISB , SUMJINT$ buffered integrating summing junction($BISJ$): Failure Mode Effects Analysis} % title of Table \label{tbl:DS2AS} \begin{tabular}{|| l | l | c | c | l ||} \hline @@ -2290,14 +2305,17 @@ $$ G^1_0 = \{ BFINT^1, SUMJ^1 \} $$ \hline \hline - FS1: $SUMJ^1$ $V_{in} DOM$ & & output integral of $V_{in}$ & & $OUTPUT STUCK$ \\ - FS2: $SUMJ^1$ $V_{fb} DOM$ & & output integral of $V_{fb}$ & & $OUTPUT STUCK$ \\ \hline - + FS1: $SUMJINT$ $V_{in} DOM$ & & output integral of $V_{in}$ & & $OUTPUT STUCK$ \\ + FS2: $SUMJINT$ $V_{fb} DOM$ & & output integral of $V_{fb}$ & & $OUTPUT STUCK$ \\ + % $$ fm(SUMJUINT^1_0) = \{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$ + FS3: $SUMJINT$ $NO\_INTEGRATION$ & & output stuck high or low & & $OUTPUT STUCK$ \\ + FS4: $SUMJINT$ $HIGH$ & & output stuck high & & $OUTPUT STUCK$ \\ + FS5: $SUMJINT$ $LOW$ & & output stuck low & & $OUTPUT STUCK$ \\ \hline %\hline - FS3: $BFINT^1$ $HIGH$ & & output perm. high & & $OUTPUT STUCK$ \\ - FS4: $BFINT^1$ $LOW$ & & output perm. low & & $OUTPUT STUCK$ \\ \hline - FS5: $BFINT^1$ $ NO\_INTEGRATION$ & & no current drive & & $OUTPUT STUCK$ \\ - FS6: $BFINT^1$ $LOW\_SLEW$ & & delayed signal & & $REDUCED\_INTEGRATION$ \\ \hline + FS6: $HISB$ $HIGH$ & & output perm. high & & $OUTPUT STUCK$ \\ + FS7: $HISB$ $LOW$ & & output perm. low & & $OUTPUT STUCK$ \\ + FS8: $HISB$ $ NO\_INTEGRATION$ & & no current drive & & $OUTPUT STUCK$ \\ + FS9: $HISB$ $LOW\_SLEW$ & & delayed signal & & $REDUCED\_INTEGRATION$ \\ \hline \hline \end{tabular} @@ -2317,40 +2335,40 @@ called $BISJ^2$. -\subsubsection{{\fg} $IC4$ and $DL2AL$} +\subsubsection{{\fg} $DL2AL$ and $DIGBUF$} %$$ fm (DL2AL^2) = \{ LOW, HIGH, LOW\_SLEW \} $$ %$$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$ -The functional group formed by $IC4$ and $DL2AL$ takes the flip flop clocked and buffered +The functional group formed by $DIGBUF$ and $DL2AL$ takes the flip flop clocked and buffered value, and outputs it at analogue voltage levels for the summing junction. -$ G^2_1 = \{ IC4^0, DL2AL^2, CLOCK\} $ +$ FG = \{ DIGBUF, DL2AL \} $ -We analyse the buffered flip flop circuitry in table~\ref{tbl:FFB}. +We analyse the buffered flip flop circuitry in table~\ref{tbl:digbuf}. \begin{table}[h+] -\caption{ $IC4^0,DL2AL^2$ flip flop buffered($FFB$): Failure Mode Effects Analysis} % title of Table -\label{tbl:FFB} +\caption{ $DIGBUF,DL2AL$ flip flop buffered($FFB$): Failure Mode Effects Analysis} % title of Table +\label{tbl:digbuf} \begin{tabular}{|| l | l | c | c | l ||} \hline %\textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ % & & & & \\ % & & & & \\ -\textbf{Failure} & & \textbf{$FFB$ } & & \textbf{Derived Component} \\ +\textbf{Failure} & & \textbf{$DIGBUF$ } & & \textbf{Derived Component} \\ \textbf{cause} & & \textbf{Effect} & & \textbf{Failure Mode} \\ \hline \hline - FS1: $IC4^0$ $HIGH$ & & output stuck high & & $OUTPUT STUCK$ \\ - FS2: $IC4^0$ $LOW$ & & output stuck low & & $OUTPUT STUCK$ \\ - FS3: $IC4^0$ $NOOP$ & & output stuck low & & $OUTPUT STUCK$ \\ \hline + FS1: $DIGBUF$ $STOPPED$ & & output stuck & & $OUTPUT STUCK$ \\ + FS2: $DIGBUF$ $LOW$ & & output stuck low & & $OUTPUT STUCK$ \\ + \\ \hline %\hline - FS4: $DL2AL^2$ $LOW$ & & output perm. high & & $OUTPUT STUCK$ \\ - FS5: $DL2AL^2$ $HIGH$ & & output perm. low & & $OUTPUT STUCK$ \\ \hline - FS6: $DL2AL^2$ $LOW\_SLEW$ & & no current drive & & $LOW\_SLEW$ \\ + FS3: $DL2AL$ $LOW$ & & output perm. high & & $OUTPUT STUCK$ \\ + FS4: $DL2AL$ $HIGH$ & & output perm. low & & $OUTPUT STUCK$ \\ \hline + FS5: $DL2AL$ $LOW\_SLEW$ & & no current drive & & $LOW\_SLEW$ \\ - FS7: $CLOCK^0$ $STOPPED$ & & output stuck & & $OUTPUT STUCK$ \\ + \hline \hline \end{tabular} @@ -2360,6 +2378,7 @@ We now collect symptoms $\{OUTPUT STUCK, LOW\_SLEW\}$ and create a {\dc} at the called $FFB^3$. +\clearpage \subsection{Final, top level {\fg} for sigma delta Converter} @@ -2402,13 +2421,13 @@ $$fm(SSDADC^4) = \{OUTPUT\_OUT\_OF\_RANGE, OUTPUT\_INCORRECT\}$$ We now show the final hierarchy in figure~\ref{fig:sdadc}. -\begin{figure}[h] - \centering - \includegraphics[width=400pt]{./CH5_Examples/sdadc.png} - % sdadc.png: 886x1134 pixel, 72dpi, 31.26x40.01 cm, bb=0 0 886 1134 - \caption{FMMD Analysis hierarchy for the {\sd}} - \label{fig:sdadc} -\end{figure} +% \begin{figure}[h] +% \centering +% \includegraphics[width=400pt]{./CH5_Examples/sdadc.png} +% % sdadc.png: 886x1134 pixel, 72dpi, 31.26x40.01 cm, bb=0 0 886 1134 +% \caption{FMMD Analysis hierarchy for the {\sd}} +% \label{fig:sdadc} +% \end{figure} \clearpage % ] diff --git a/submission_thesis/style.tex b/submission_thesis/style.tex index 7adbfbd..c3dc659 100644 --- a/submission_thesis/style.tex +++ b/submission_thesis/style.tex @@ -31,8 +31,8 @@ \newcommand{\permil}{\ensuremath{0/{\!}_{00}}} %\newcommand{\emp}{ELECTRO MAGNETIC FUKING PULSE} \newcommand{\emp}{} %% was italics -%\newcommand{\sd}{\ensuremath{\Sigma \Delta ADC}} -\newcommand{\sd}{\ensuremath{Sigma\;Delta\;ADC}} +\newcommand{\sd}{\ensuremath{\Sigma \Delta ADC}} +%\newcommand{\sd}{\ensuremath{Sigma\;Delta\;ADC}} \newcommand{\derivec}{{D}} \newcommand{\abslev}{\ensuremath{\alpha}} \newcommand{\oc}{\ensuremath{^{o}{C}}}