From b46bcd00d92cffae3a4ad257272f39820071765d Mon Sep 17 00:00:00 2001 From: Robin Clark Date: Tue, 8 May 2012 21:43:41 +0100 Subject: [PATCH] tring to finish the sigma delta analysis, keeps becoming 10pm too quickly --- submission_thesis/CH4_FMMD/copy.tex | 6 +- submission_thesis/CH5_Examples/Makefile | 3 +- submission_thesis/CH5_Examples/copy.tex | 194 +++++++++++++++---- submission_thesis/CH5_Examples/sigdel1.dia | Bin 0 -> 2858 bytes submission_thesis/appendixes/algorithmic.tex | 9 +- 5 files changed, 163 insertions(+), 49 deletions(-) create mode 100644 submission_thesis/CH5_Examples/sigdel1.dia diff --git a/submission_thesis/CH4_FMMD/copy.tex b/submission_thesis/CH4_FMMD/copy.tex index 4e7a9c1..b67981a 100644 --- a/submission_thesis/CH4_FMMD/copy.tex +++ b/submission_thesis/CH4_FMMD/copy.tex @@ -51,9 +51,9 @@ paper { chapter } -starts with a worked example of the new methodology Failure Mode Modular De-composition (FMMD), and then -describes the data types and concepts for the method, using these a UML class model is built -and then notation is developed. +starts with a worked example using the new methodology, Failure Mode Modular De-composition (FMMD), and then +develops an ontological structure for the methodology using UML class models. +A notation is then described to index and classify objects created in FMMD models. diff --git a/submission_thesis/CH5_Examples/Makefile b/submission_thesis/CH5_Examples/Makefile index 2749f47..db75384 100644 --- a/submission_thesis/CH5_Examples/Makefile +++ b/submission_thesis/CH5_Examples/Makefile @@ -4,7 +4,8 @@ PNG_DIA = blockdiagramcircuit2.png bubba_oscillator_block_diagram.png circuit1 dubsim1.png invamp.png mvampcircuit.png pd.png plddouble.png plddoublesymptom.png \ poss1finalbubba.png poss2finalbubba.png pt100.png pt100_doublef.png pt100_singlef.png \ pt100_tc.png pt100_tc_sp.png shared_component.png stat_single.png three_tree.png \ - tree_abstraction_levels.png vrange.png sigma_delta_block.png ftcontext.png ct1.png hd.png + tree_abstraction_levels.png vrange.png sigma_delta_block.png ftcontext.png ct1.png hd.png \ + sigdel1.png diff --git a/submission_thesis/CH5_Examples/copy.tex b/submission_thesis/CH5_Examples/copy.tex index 82bbebf..05ce82f 100644 --- a/submission_thesis/CH5_Examples/copy.tex +++ b/submission_thesis/CH5_Examples/copy.tex @@ -1706,7 +1706,7 @@ and fed into the summing integrator completing the negative feedback loop. The partslist for the $\Sigma \Delta $ADC -$$\{ IC1, IC2, IC3 IC4 \} $$. +$$\{ IC1, IC2, IC3, IC4, R1, R2, R3, R4, C1 \} $$. IC1,2 and 3 are all Op-amps and we have failure modes from section~\ref{sec:opampfm}. @@ -1722,8 +1722,12 @@ The resistors and capacitor failure modes we take from EN298~\cite{en298}[An.A] $$ fm ( R ) = \{OPEN, SHORT\} $$ -$$ fm ( C) = \{OPEN, SHORT\} $$ +$$ fm ( C ) = \{OPEN, SHORT\} $$ + +\subsection{Identifying initial {\fgs}} + +\subsubsection{Summing Junction} We now need to choose {\fgs}. The signal path is circular, but we can start with the input voltage, which is applied to $R2$, we can term this voltage $V_{in}$. $R2$ and $R1$ form a summing junction to IC1. @@ -1732,7 +1736,7 @@ This can be our first {\fg}. For the symptoms, we have to think in terms of the on its performance as a summing junction and not be distracted by the integrator formed by $C_1$ and $IC1$. -$$G^0_1 = \{R1, R2\}$$ +$$G^0_1 = \{R1, R2 \}$$ \begin{table}[h+] \caption{R1,R2 Summing Junction: Failure Mode Effects Analysis} % title of Table @@ -1757,15 +1761,21 @@ From the analysis in table~\ref{tbl:sumj}, we can now create a derived component $SUMJ$ which has the failure modes from collecting its symptoms. We can state -$$ fm(SUMJ) = \{ V_{in} DOM, V_{in} DOM \} $$ +$$ fm(SUMJ) = \{ V_{in} DOM, V_{fb} DOM \} $$ +\subsubsection{Buffered Integrator} -Following along the signal path, the next functional group is the integrator. -This integrator is simply by $IC2$. This performs the function of -isolating the integrator from any load on its output. We can therefore include this as well. +Following the signal path, the next functional group is the integrator. +This integrator is formed by $C$ by $IC2$\cite{aoe}[ch.4]. +The output of the integrator is fed into IC2, which acts as a buffer. +%performing the function of +isolating the integrator from any load on its output. +These three components work together to form a buffered integrator, +and nicely form a {\fg}. -$$G^0_2 = \{IC1, C1, IC2\}$$ +$$G^0_2 = \{IC1, C1, IC2\}.$$ +The buffered integrator is analysed in table~\ref{tbl:intg}. \begin{table}[h+] @@ -1796,10 +1806,111 @@ $$G^0_2 = \{IC1, C1, IC2\}$$ From the analysis in table~\ref{tbl:intg}, we can now create a derived component -$SUMJ$ which has the failure modes from collecting its symptoms. +$BFINT$ which has the failure modes from collecting symptoms from the analysis in table~\ref{tbl:intg}. We can state -$$ fm (SUMJ) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ +$$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ + + + + + + +\subsubsection{Digital level to analogue level conversion ($DL2AL$).} +Digital level to analogue level conversion is performed by IC3 in conjunction with a potential divider formed by R3,R4. +The potential divider provides a mid rail reference voltage +to the inverting input of IC3. + +\paragraph{Potential divider Formed by R3,R4.} +We re-use the analysis from section~\ref{sec:pd}, and used the derived component $PD$ +to represent the potential divider formed by R3 and R4. Because PD is a derived component, we can denote this +by super-scripting it with its abstraction level of 1, thus $PD^1$. +$$ +fm(PD^1) = \{ HIGH, LOW \}. +$$ + +IC3 is an op-amp and has the failure modes +$$fm(IC3) = \{\{ HIGH, LOW, NOOP, LOW\_SLEW \} . $$ + +The digital signal is supplied to the non-inverting input. +The output is a voltage level in the analogue domain $-V$ or $+V$. + +We now form a {\fg} from $PD^1$ and $IC3$. + +$$ G^1 = \{ PD^1, IC3 \} $$ + +We now analyse the {\fg} $G^1$ in table~\ref{tbl:DS2AS}. + +\begin{table}[h+] +\caption{$PD^1, IC3$ Digital level to analogue level converter: Failure Mode Effects Analysis} % title of Table +\label{tbl:DS2AS} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + & & & & \\ + \hline \hline + FS1: $PD^1$ $HIGH$ & & output perm. low & & LOW \\ + FS2: $PD^1$ $LOW$ & & output perm. low & & HIGH \\ \hline + +\hline + FS3: $IC3$ $HIGH$ & & output perm. high & & HIGH \\ + FS4: $IC3$ $LOW$ & & output perm. low & & LOW \\ \hline + FS5: $IC3$ $NOOP$ & & no current drive & & LOW \\ + FS6: $IC3$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline +\hline + +\end{tabular} +\end{table} + +We collect the symptoms of failure $\{ LOW, HIGH, LOW\_SLEW \}$. +We can now derive a new component to represent the level conversion and call it $DL2AL$. + +$$ DL2AL = D(G^1) $$ + +$$ fm (DL2AL) = \{ LOW, HIGH, LOW\_SLEW \} $$ + + + + +\subsubsection{digital clocked memory (flip-flop).} + +This is a single component as a {\fg}, and we can state +$$ fm (DCM) = \{ HIGH, LOW, NOOP \} $$ + + +\subsection{First {\fgs} analysed} + +We have analysed the initial {\fgs} and can now take stock of the situation +and see what is now required. Figure~\ref{fig:sigdel1} shows how far the +hierarchy has been built. + + +\begin{figure}[h+] + \centering + \includegraphics[width=400pt]{./CH5_Examples/sigdel1.png} + % sigdel1.png: 766x618 pixel, 72dpi, 27.02x21.80 cm, bb=0 0 766 618 + \caption{First stage of FMMD analysis: Sigma delta Converter} + \label{fig:sigdel1} +\end{figure} + + +IC4 is as yet unused, the signal path connects IC4 and DL2AL. These seem natural candidates +for the next {\fg}. +BFINT and SUMJ are adjacent in the signal path and these are chosen as a {\fg} as well. + + +\subsubsection{{\fg} BFINT and SUMJ} +\subsubsection{{\fg} IC4 and DL2AL} + + +\subsection{Final, top level {\fg} for sigma delta Converter} + + + + + + + % ] % into % @@ -1819,40 +1930,41 @@ $$ fm (SUMJ) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ % and IC3. % The output from this is sent to the summing integrator as the signal summed with the input. -\subsection{Identifying initial {\fgs}} - -\subsubsection{Summing Junction formed by R1 and R2} - -The resistors R1, R2 form a summing junction -to the negative input of IC1. -Using the earlier definition for resistor failure modes, -$fm(R)= \{OPEN, SHORT\}$, we analyse the summing junction -in table~\ref{tbl:sumjunct} below. - -\begin{table}[h+] -\caption{Summing Junction: Failure Mode Effects Analysis: Single Faults} % title of Table -\label{tbl:sumjunct} - -\begin{tabular}{|| l | l | c | c | l ||} \hline - \textbf{Failure Scenario} & & \textbf{Summing} & & \textbf{Symptom} \\ - & & \textbf{Junction} & & \\ - \hline - FS1: R1 SHORT & & R1 input dominates & & $R1\_IN\_DOM$ \\ \hline - FS2: R1 OPEN & & R2 input dominates & & $R2\_IN\_DOM$ \\ \hline - FS3: R2 SHORT & & R2 input dominates & & $R2\_IN\_DOM$ \\ \hline - FS4: R2 OPEN & & R1 input dominates & & $R1\_IN\_DOM$ \\ \hline - -\hline - -\end{tabular} -\end{table} -% PHS45 - -This summing junction fails with two symptoms. We create a {\dc} called $SUMJUNCT$ and we can state, -$$fm(SUMJUNCT) = \{ R1\_IN\_DOM, R2\_IN\_DOM \} $$. + +% The resistors R1, R2 form a summing junction +% to the negative input of IC1. +% Using the earlier definition for resistor failure modes, +% $fm(R)= \{OPEN, SHORT\}$, we analyse the summing junction +% in table~\ref{tbl:sumjunct} below. +% +% \begin{table}[h+] +% \caption{Summing Junction: Failure Mode Effects Analysis: Single Faults} % title of Table +% \label{tbl:sumjunct} +% +% \begin{tabular}{|| l | l | c | c | l ||} \hline +% \textbf{Failure Scenario} & & \textbf{Summing} & & \textbf{Symptom} \\ +% & & \textbf{Junction} & & \\ +% \hline +% FS1: R1 SHORT & & R1 input dominates & & $R1\_IN\_DOM$ \\ \hline +% FS2: R1 OPEN & & R2 input dominates & & $R2\_IN\_DOM$ \\ \hline +% FS3: R2 SHORT & & R2 input dominates & & $R2\_IN\_DOM$ \\ \hline +% FS4: R2 OPEN & & R1 input dominates & & $R1\_IN\_DOM$ \\ \hline +% +% \hline +% +% \end{tabular} +% \end{table} +% % PHS45 +% +% This summing junction fails with two symptoms. We create a {\dc} called $SUMJUNCT$ and we can state, +% $$fm(SUMJUNCT) = \{ R1\_IN\_DOM, R2\_IN\_DOM \} $$. + + +The D type flip flop + %\subsection{FMMD Process applied to $\Sigma \Delta $ADC}. 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We can then go further and consider these to -be symptoms of failures in the components of the {\fg}. -We can collect common symptoms of failure for the {\fg}. +be symptoms of failure of the {\fg}. +Because component failures will often manifest themselves as the same symptoms of failure, +we are able to collect common symptoms of failure for the {\fg}. % % With the collected common symptoms, we can treat the {\fg} @@ -37,7 +38,7 @@ Once a hierarchy is in place, it can be converted into a fault data model. \fmmdgloss % From the fault data model, automatic generation -of FTA \cite{nasafta} (Fault Tree Analysis) and mimimal cuts sets \cite{nucfta} are possible. +of FTA \cite{nasafta} (Fault Tree Analysis) and minimal cuts sets \cite{nucfta} are possible. Also statistical reliability/probability of failure~on~demand \cite{en61508} and MTTF (Mean Time to Failure) calculations can be produced automatically\footnote{Where component failure mode statistics are available \cite{mil1991}}. % @@ -315,7 +316,7 @@ aircraft.}) of the failure modes to form `test cases'. \item If required, create test cases from all valid double failure mode combinations within the {\fg}. % \item Draw these as contours on a diagram -% \item Where si,ultaneous failures are examined use overlapping contours +% \item Where simultaneous failures are examined use overlapping contours % \item For each region on the diagram, make a test case \item Using the `test cases' as scenarios to examine the effects of component failures, we determine the failure~mode behaviour of the functional group.