diff --git a/components_as_plds/components_as_plds.tex b/components_as_plds/components_as_plds.tex
index 2334e08..b225b24 100644
--- a/components_as_plds/components_as_plds.tex
+++ b/components_as_plds/components_as_plds.tex
@@ -77,19 +77,47 @@ It could be overstressed and burnt out, (by the application of an out of spec cu
 Resistors typically drift slightly in value with temperature. For some applications this may not be important.
 The manufacturers data-sheet will describe the temperature drift co-effecients and operating ranges.
 
-We can represent our resistor then to be in four operational states, $R_s = \{ OK, OPEN, SHORT, T\_DRIFT \}$.
+\paragraph{discusion on $P\_CHANGE$ as a resistor failure mode.}
+HERE reference EN298 and RAC.
+Talk about the differences, why en298 only looks for OPEN in most cases
+and OPEN AND SHORT in one but not $P\_CHANGE$ .
+RAC gives $P\_CHANGE$ for single resistors but not for resistor networks.
+It is interesting to determine why this is.
+A network of resistors would be less prone to batch
+problems where a parameter drift would all be in the sam direction (with age perhaps)
+.
+But also a network of resistors means a load sharing where resistors will be
+under less electrical stress.
+
+This is because components in EN298 must be 60\% under any environemntal electrical or mechanical
+stress safe rating as given by a manufacturer.
+Thus a resistor rated for 50V would not be allowed in a ciruit with a 100V rail,
+even though in normal operation, the resistor would never have more than say 30V applied to it.
+
+For most safety critical applications components are downrated, and for resistors this means $P\_CHANGE$
+does not have to be cosidered.
+
+
+We can represent our resistor then to be in four operational states, $R_s = \{ OK, OPEN, SHORT, P\_CHANGE \}$.
 Because we are interested in failure analysis we assume that every component has an OK state
 but this is not of interest. When every component on a board is in the $OK$ state 
 the sub-system will function correctly.
 We are interested in failures and how that affects the sub-system, so we 
 can ignore the $OK$ state and represent our resistor thus for the purpose of fault analysis.
 
- $$R_s = \{ OPEN, SHORT, T\_DRIFT \}$$
+ $$R_s = \{ OPEN, SHORT, P\_CHANGE \}$$
 
 
 This can be represented in a PLD thus 
  IMAGE HERE
 
+For a resistor in a safety critical regime demanding rigorous downrating, we can model our
+rsistor with 
+
+IMAGE HERE
+$$R_s = \{ OPEN, SHORT \}$$
+
+
 \section{ PNP Transistor }
 
 Each leg open : each leg shorted all combinations.
diff --git a/logic_diagram/logic_diagram.tex b/logic_diagram/logic_diagram.tex
index ab8f263..5f88a89 100644
--- a/logic_diagram/logic_diagram.tex
+++ b/logic_diagram/logic_diagram.tex
@@ -555,7 +555,7 @@ of $ R = b \oplus c $.
 
 \begin{figure}[h]
  \centering
- \includegraphics[width=250pt,keepaspectratio=true]{./ldmeq2.jpg}
+ \includegraphics[width=250pt,keepaspectratio=true]{logic_diagram/ldmeq2.jpg}
  % ldmeq2.jpg: 572x297 pixel, 72dpi, 20.18x10.48 cm, bb=0 0 572 297
  \caption{Labels in PLD diagrams}
  \label{fig:ld_meq2}