typos and a rough draft of the conclusion
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@ -1490,59 +1490,22 @@ and ram complement checking can be applied.
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\section{Conclusion}
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\section{Conclusion}
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This paper has picked a very simple example (the industry standard {\ft}
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Effeciency --- the $O(N^2)$ has been broken down by making it
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input circuit and software)
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several much easier to deal with $O(n^2)$ analyis stages.
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to demonstrate
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SFMEA and HFMEA methodologies used to describe a failure mode model.
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Even a modest system would be far too large to analyse in conference paper
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and this
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The {\dc} representing the {\ft} reader
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While there are no FMEA metrics to compare a sw hw hybrid
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shows that by taking a
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using FMMD an estimate of the work to perform, the reasoning distance, can be calculated.
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modular approach for FMEA, i.e. FMMD, we can integrate
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Our model is described by four FMEA reports; and these % we can model the failure mode behaviour from
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model the system from several failure mode perspectives.
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With traditional FMEA methods the reasoning~distance is large, because
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it stretches from the component failure mode to the top---or---system level failure.
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With these four analysis reports
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we do not have stages along the `reasoning~path' linking the failure modes from the
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electronics to those in the software.
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Software is often written `defensively' but t
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Each {\fg} to {\dc} transition represents a
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reasoning stage.
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For this reason applying traditional FMEA to software stretches
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hw sw interface is handled naturally. Any hw failures
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the reasoning distance even further.
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can now no longer be missed or forgotten in the analysis process.
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The sw faces no suprise hw errors that it has no sensible
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way of dealing with.
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In fact many these reasoning paths overlap---or even by-pass one another---
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Errors introduced by the uP are unresolved in this example. But they are listed.
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it is very difficult to gauge cause and effect.
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For instance, hardware failures are not analysed in the context of how they will
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be handled (or missed) by the software.
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System outputs commanded from software may not take into account particular
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hardware limitations etc.
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The interface FMEA does serve to provide a useful
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check-list to ensure data and synchronisation conventions used by the hardware
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and software are not mismatched. However, the fact it is perceived as required
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highlights the the miss-matches possible between the two types of analysis
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which could run deeper than the mere interface level.
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However, while these techniques ensure that the software and hardware is
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Re-useability --- the electronics --- the Pt100 --- s/w functions to read ADC values
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viewed and analysed from several perspectives, it cannot be termed a homogeneous
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failure mode model.
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For instance
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were the ADC to have a small value error, say adding
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a small percentage onto the value, we would be unable to
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detect this under the analysis conditions for this model, or
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be able to pinpoint it.
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Need wishlist ticks and solved problems here.
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{
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{
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\footnotesize
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\footnotesize
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