Sigma Delta tidied up.

Chris Garret rightly pointed out
that the two resistors could not be considered
as a summing junction on their own because
they connnected to the -ve input of the integrating OpAmp.
Changed structure of the FMMD analysis accordingly.

mybib.bib

@@ -323,7 +323,12 @@ year = {2012},
   PUBLISHER =      "Newnes",
   YEAR =         "2002"
 }
-
+@BOOK{ehb,
+  AUTHOR =       "Jerry C whitaker",
+  TITLE =        "The Electronics Handbook ISBN:0-8493-8345-5   ",
+  PUBLISHER =      "IEEE Press ",
+  YEAR =         "1996"
+}
 @BOOK{alggraph,
   AUTHOR =       "Alan Gibbons",
   TITLE =        "Algorithmic Graph Theory ISBN:978-0521288811   ",

submission_thesis/CH5_Examples/Makefile

@@ -5,7 +5,7 @@ PNG_DIA = blockdiagramcircuit2.png  bubba_oscillator_block_diagram.png  circuit1
 	poss1finalbubba.png   poss2finalbubba.png   pt100.png   pt100_doublef.png   pt100_singlef.png       \
 	pt100_tc.png         pt100_tc_sp.png      shared_component.png   stat_single.png    three_tree.png  \
 	tree_abstraction_levels.png   vrange.png sigma_delta_block.png ftcontext.png ct1.png hd.png         \
-        sigdel1.png sdadc.png bubba_euler_1.png bubba_euler_2.png eulersd.png
+        sigdel1.png sdadc.png bubba_euler_1.png bubba_euler_2.png eulersd.png eulersdfinal.png
 
 
 

submission_thesis/CH5_Examples/copy.tex

@@ -1207,7 +1207,7 @@ to periodically switch in test signals in place of the input signal.}
 
 The circuit in figure~\ref{fig:circuit2} shows a five pole low pass filter.
 Starting at the input, we have a first order low pass filter buffered by an op-amp, 
-the output of this is passed to a Sallen~Key~\cite{aoe}[p.267] second order lowpass filter.
+the output of this is passed to a Sallen~Key~\cite{aoe}[p.267]~\cite{electronicssysapproach}[p.288] second order low-pass filter.
 The output of this is passed into another Sallen~Key filter -- which although it may have different values
 for its resistors/capacitors and thus have a different frequency response -- is identical from a failure mode perspective.
 Thus we can analyse the first Sallen~Key low pass filter and re-use the results for the second stage
@@ -1983,6 +1983,8 @@ The output of the flip flop is also routed to the feedback.
 It is level converted to an analogue signal
 (i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage)
 and fed into the summing integrator completing the negative feedback loop.
+%
+This implements an over-sampling analogue to digital converter~\cite{ehb}[pp.729-730].
 
 \subsection{FMMD analysis of \sd }
 
@@ -2076,9 +2078,9 @@ We  create the derived component
 $SUMJINT$ and assign it the failure modes collected above.% which has the failure modes from collecting its symptoms.
 We now state:
 
-$$ fm(SUMJUINT^1_0) = \{ V_{in} DOM, V_{fb} DOM,  NO\_INTEGRATION,  HIGH, LOW  \} .$$
+$$ fm(SUMJUINT) = \{ V_{in} DOM, V_{fb} DOM,  NO\_INTEGRATION,  HIGH, LOW  \} .$$
 
-That is the failure modes of our new {\dc} $SUMJINT^1_0$ are $\{ V_{in} DOM, V_{fb} DOM,  NO\_INTEGRATION,  HIGH, LOW  \} .$
+That is the failure modes of our new {\dc} $SUMJINT$ are $$\{ V_{in} DOM, V_{fb} DOM,  NO\_INTEGRATION,  HIGH, LOW  \} .$$
 
 \clearpage
 
@@ -2122,9 +2124,11 @@ we my consider it as a derived component, that of a High Impedance Signal Buffer
 % 
 % \end{tabular}
 % \end{table} 
-We create the {\dc} $HISB^1_1$ and it failure mode may be stated as $fm(HISB^1_1) = \{HIGH, LOW, NOOP, LOW_{SLEW} \}$.
+We create the {\dc} $HISB$ and its failure mode may be stated as $$fm(HISB) = \{HIGH, LOW, NOOP, LOW_{SLEW} \}$$.
 
 \subsubsection{Digital level to analogue level conversion ($DL2AL$).}
+The integrator is implemented in digital electronics, but the output from the D type flip flop is a digital signal.
+A conversion stage is required to interface these stages.
 Digital level to analogue level conversion is performed by IC3 in conjunction with  a potential divider formed by R3,R4.
 The potential divider provides a mid rail reference voltage
 to the inverting input of IC3.
@@ -2181,7 +2185,7 @@ We can now derive a new component to represent the level conversion and call it
 
 $$ DL2AL  = D(FG  = \{ PD , IC3 \}) $$
 
-$$ fm (DL2AL^2) = \{ LOW, HIGH,  LOW\_{SLEW}  \} $$
+$$ fm (DL2AL) = \{ LOW, HIGH,  LOW\_{SLEW}  \} $$
 
 \clearpage
 
@@ -2228,7 +2232,7 @@ We now analyse this {\fg}   in table~\ref{tbl:digbuf}.
 \end{table} 
 
 We collect the symptoms of failure $\{ LOW, STOPPED  \}$.
-We can now derive a new component to represent the level conversion and call it $DIGBUF$.
+We can now derive a new component to represent the digital buffer  and call it $DIGBUF$.
 
 
 $$ fm (DIGBUF) = \{ LOW, STOPPED  \} $$
@@ -2251,9 +2255,11 @@ These are:
  \item DL2AL --- A digital to analog level converter.
  \item DIGBUF --- A digital one bit buffer/memory
 \end{itemize}
-These {\dcs} follow to signal path shown in figure~\ref{fig:sigmadeltablock}.
+These {\dcs} follow the signal path shown in figure~\ref{fig:sigmadeltablock}.
-We now use these {\dcs} to create a final {\fg} to represent the failure mode
+We now use these {\dcs} to create higher level  {\fgs}.
-behaviour of the $\Sigma \Delta ADC$. We represent this
+%to represent the failure mode
+%behaviour of the $\Sigma \Delta ADC$. 
+We represent this
 in the Euler diagram in figure~\ref{fig:eulersd}.
 The next stage is to create {\fgs} from these initial {\dcs}
 and make a complete failure mode mode for the {\sd}.
@@ -2262,7 +2268,7 @@ and make a complete failure mode mode for the {\sd}.
  \centering
  \includegraphics[width=400pt]{./CH5_Examples/eulersd.png}
  % eulersd.png: 1018x334 pixel, 72dpi, 35.91x11.78 cm, bb=0 0 1018 334
- \caption{Euler diagram showing the functional grouping used to model the $\Sigma \Delta ADC$}
+ \caption{Euler diagram showing the initial {\dcs} used to model the $\Sigma \Delta ADC$}
  \label{fig:eulersd}
 \end{figure}
 
@@ -2276,10 +2282,6 @@ and make a complete failure mode mode for the {\sd}.
 % \end{figure}
 
  
-%IC4 is as yet unused, the signal path connects IC4 and DL2AL. These seem natural candidates
-%for the next {\fg}.
-BFINT and SUMJ are adjacent in the signal path and these are chosen as a {\fg} as well.
-
 \clearpage
 
 
@@ -2323,8 +2325,8 @@ $$ FG  = \{ HISB, SUMJINT \} $$
 
 
 
-We now collect symptoms $\{  OUTPUT STUCK  ,  REDUCED\_INTEGRATION \}$, and create a {\dc}
+We now collect the symptoms of failure $\{  OUTPUT STUCK  ,  REDUCED\_INTEGRATION \}$, and create a {\dc}
-called $BISJ^2$.
+called $BISJ$.
 
 
 
@@ -2374,24 +2376,26 @@ We analyse the buffered flip flop circuitry in table~\ref{tbl:digbuf}.
 \end{tabular}
 \end{table} 
 
-We now collect symptoms $\{OUTPUT STUCK, LOW\_SLEW\}$ and create a {\dc} at the third level of symptom abstraction
+We now collect symptoms $\{OUTPUT STUCK, LOW\_SLEW\}$ and create a {\dc} %at the third level of symptom abstraction
-called $FFB^3$.
+called $FFB$.
 
 
 \clearpage
 \subsection{Final, top level {\fg} for sigma delta Converter}
 
 
-We now have two {\dcs}, $FFB^3$ and $BISJ^2$: we form a final functional group with these:
+We now have two {\dcs}, $FFB$ and $BISJ$.
-$$ G^3_0 = \{ FFB^3, BISJ^2 \} .$$
+These together represent all base components within this circuit.
-We analyse the buffered {\sd} circuit in table~\ref{tbl:FFB}.
+We form a final functional group with these:
+$$ FG  = \{ FFB , BISJ  \} .$$
+We analyse the buffered {\sd} circuit in table~\ref{tbl:sdadc}.
 %
 % FFB^3 $\{OUTPUT STUCK, LOW\_SLEW\}$
 % BISJ^2 $\{  OUTPUT STUCK  ,  REDUCED\_INTEGRATION \}$
 %
 \begin{table}[h+]
-\caption{ $FFB^3, BISJ^2$ \sd ($SDADC$): Failure Mode Effects Analysis} % title of Table
+\caption{ $FFB , BISJ $ \sd ($SDADC$): Failure Mode Effects Analysis} % title of Table
-\label{tbl:sd}
+\label{tbl:sdadc}
 
 \begin{tabular}{|| l | l | c | c | l ||} \hline
  %\textbf{Failure Scenario} & &  \textbf{failure result }         &   & \textbf{Symptom}          \\ 
@@ -2401,12 +2405,12 @@ We analyse the buffered {\sd} circuit in table~\ref{tbl:FFB}.
  \textbf{cause}   & &  \textbf{Effect}    &   & \textbf{Failure Mode}          \\
                                
                \hline \hline 
-  FS1: $FFB^3$  $OUTPUT STUCK$                      &  &   value max high or low          &  &    $OUTPUT\_OUT\_OF\_RANGE$            \\    
+  FS1: $FFB$  $OUTPUT STUCK$                      &  &   value max high or low          &  &    $OUTPUT\_OUT\_OF\_RANGE$            \\    
-  FS2: $FFB^3$  $LOW\_SLEW$                         &  &   values will appear larger      &  &    $OUTPUT\_INCORRECT$                  \\   
+  FS2: $FFB$  $LOW\_SLEW$                         &  &   values will appear larger      &  &    $OUTPUT\_INCORRECT$                  \\   
 %   FS3: $IC4^0$ $NOOP$         &  &     output stuck low           &  &    $OUTPUT STUCK$                  \\ \hline 
 %\hline 
-  FS3: $BISJ^2$  $OUTPUT STUCK$                     &  &    value max high or low         &  &     $OUTPUT\_OUT\_OF\_RANGE$             \\    
+  FS3: $BISJ$  $OUTPUT STUCK$                     &  &    value max high or low         &  &     $OUTPUT\_OUT\_OF\_RANGE$             \\    
-  FS4: $BISJ^2$  $REDUCED\_INTEGRATION$             &  &    values will appear larger         &  &     $OUTPUT\_INCORRECT$              \\   \hline 
+  FS4: $BISJ$  $REDUCED\_INTEGRATION$             &  &    values will appear larger         &  &     $OUTPUT\_INCORRECT$              \\   \hline 
   
   
 \hline
@@ -2417,10 +2421,16 @@ We analyse the buffered {\sd} circuit in table~\ref{tbl:FFB}.
 We now collect the symptoms for the \sd $ \; 
 \{OUTPUT\_OUT\_OF\_RANGE, OUTPUT\_INCORRECT\}$.
 We can now create a {\dc} to represent the analogue to digital converter, $SADC^4$.
-$$fm(SSDADC^4) = \{OUTPUT\_OUT\_OF\_RANGE, OUTPUT\_INCORRECT\}$$
+$$fm(SSDADC) = \{OUTPUT\_OUT\_OF\_RANGE, OUTPUT\_INCORRECT\}$$
-We now show the final hierarchy in figure~\ref{fig:sdadc}.
+We now show the   final {\dc} hierarchy in figure~\ref{fig:eulersdfinal}.
-
 
+\begin{figure}[h]
+ \centering
+ \includegraphics[width=400pt]{./CH5_Examples/eulersdfinal.png}
+ % eulersd.png: 1018x334 pixel, 72dpi, 35.91x11.78 cm, bb=0 0 1018 334
+ \caption{Euler diagram showing the final {\dcs} used to model the $\Sigma \Delta ADC$}
+ \label{fig:eulersdfinal}
+\end{figure}
 % \begin{figure}[h]
 %  \centering
 %  \includegraphics[width=400pt]{./CH5_Examples/sdadc.png}