Merge branch 'master' of dev:/home/robin/git/thesis
This commit is contained in:
commit
7fbd52c2ba
@ -6,6 +6,7 @@ PNG = fmmdh.png ct1.png hd.png ftcontext.png
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all: ${PNG}
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pdflatex software_fmea
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pdflatex software_fmea
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acroread software_fmea.pdf
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|
@ -135,7 +135,7 @@ failure mode of the component or sub-system}}}
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%
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Failure Mode Effects Analysis (FMEA), is a is a bottom-up technique that aims to assess the effect all
|
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component failure modes on a system.
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It is used both as a design tool (to determine weakness), and is a requirement of certification of safety critical products.
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It is used both as a design tool (to determine weaknesses), and is a requirement of certification of safety critical products.
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FMEA has been successfully applied to mechanical, electrical and hybrid electro-mechanical systems.
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Work on software FMEA is beginning, but
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|
@ -1,15 +1,15 @@
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PNG_DIA = cfg2.png cfg.png compco2.png compco3.png compco.png component.png componentpl.png fmmd_uml2.png fmmd_uml.png partitioncfm.png master_uml.png
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PNG_DIA = cfg2.png cfg.png compco2.png compco3.png compco.png component.png componentpl.png fmmd_uml2.png fmmd_uml.png partitioncfm.png master_uml.png top_down_de_comp.png
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%.png:%.dia
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dia -t png $<
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echo " Chapter 4 DIA images generated"
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pdf: $(PNG_DIA)
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pdflatex discussion_doc
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acroread discussion_doc.pdf &
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#pdf: $(PNG_DIA)
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# pdflatex discussion_doc
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# acroread discussion_doc.pdf &
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# this is the target used
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|
File diff suppressed because it is too large
Load Diff
BIN
submission_thesis/CH4_FMMD/top_down_de_comp.dia
Normal file
BIN
submission_thesis/CH4_FMMD/top_down_de_comp.dia
Normal file
Binary file not shown.
@ -3,6 +3,7 @@
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This chapter demonstrates FMMD applied to
|
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a variety of common electronic circuits.
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In order to implement FMMD in practise, we review the basic concepts and processes of the methodology.
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\section{Basic Concepts Of FMMD}
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@ -60,7 +61,7 @@ Failure modes for part types can be found in the literature~\cite{fmd91}\cite{mi
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\subsection{Determining the failure modes of components}
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\label{sec:determine_fms}
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In order to apply any form of Failure Mode Effects Analysis (FMEA) we need to know the ways in which the components we are using can fail.
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Typically when choosing components for a design, we look at manufacturers' data sheets,
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which describe the environmental ranges and tolerances, and can indicate how a component may fail/behave
|
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@ -195,7 +196,8 @@ and thus subject to drift/parameter change.
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%In a system designed to typical safety critical constraints (as in EN298)
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%these environmentally induced failure modes need not be considered.
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\subsubsection{Resistor Failure Modes}
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\label{sec:res_fms}
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For this study we will take the conservative view from EN298, and consider the failure
|
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modes for a generic resistor to be both OPEN and SHORT.
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i.e.
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@ -244,10 +246,10 @@ a signal may be lost.
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We can map this failure cause to a {\fm}, and we can call it $LOW_{slew}$.
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\paragraph{No Operation - over stress}
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Here the OP\_AMP has been damaged, and the output may be held HIGH LOW, or may be effectively tri-stated
|
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Here the OP\_AMP has been damaged, and the output may be held HIGH or LOW, or may be effectively tri-stated
|
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, i.e. not able to drive circuitry in along the next stages of the signal path: we can call this state NOOP (no Operation).
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%
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We can map this failure cause to three symptoms, $LOW$, $HIGH$, $NOOP$.
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We can map this failure cause to three {\fms}, $LOW$, $HIGH$, $NOOP$.
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\paragraph{Shorted $V_+$ to $V_-$}
|
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Due to the high intrinsic gain of an op-amp, and the effect of offset currents,
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@ -339,10 +341,18 @@ and determine its {\fms}.
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%\clearpage
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\subsubsection{Failure modes of an OP-AMP}
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\label{sec:opamp_fms}
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For the purpose of the examples to follow, the op-amp will
|
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have the following failure modes:-
|
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|
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$$ fm(OPAMP) = \{ LOW, HIGH, NOOP, LOW_{slew} \} $$
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\subsection{Comparing the component failure mode sources}
|
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|
||||
|
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The EN298 pinouts failure mode technique cannot reveal failure modes due to internal failures.
|
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The FMD-91 entires for op-amps are not directly usable as
|
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component {\fms} in FMEA or FMMD and require interpretation.
|
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@ -350,10 +360,6 @@ component {\fms} in FMEA or FMMD and require interpretation.
|
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%For our OP-AMP example could have come up with different symptoms for both sides. Cannot predict the effect of internal errors, for instance ($LOW_{slew}$)
|
||||
%is missing from the EN298 failure modes set.
|
||||
|
||||
For the purpose of the examples to follow, the op-amp will
|
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have the following failure modes:-
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|
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$$ fm(OPAMP) = \{ LOW, HIGH, NOOP, LOW_{slew} \} $$
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||||
|
||||
% FMD-91
|
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%
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||||
@ -441,7 +447,7 @@ We can now treat $AMP1$ as a pre-analysed, higher level component.
|
||||
The amplifier is an abstract concept, in terms of the components.
|
||||
To a make an `amplifier' we have to connect a a group of components
|
||||
in a specific configuration. This specific configuration corresponds to
|
||||
a {\fg}. Our use of it as a building block corresponds to a {\dc}.
|
||||
a {\fg}. Our use of it as a subsequent building block corresponds to a {\dc}.
|
||||
|
||||
|
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%What this means is the `fault~symptoms' of the module have been derived.
|
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@ -540,13 +546,14 @@ We can now create a {\dc} for the potential divider, $PD$.
|
||||
|
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$$ fm(PD) = \{ PDLow, PDHigh \}$$
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|
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Let us now consider the op-amp. According to
|
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FMD-91~\cite{fmd91}[3-116] an op-amp may have the following failure modes:
|
||||
latchup(12.5\%), latchdown(6\%), nooperation(31.3\%), lowslewrate(50\%).
|
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%Let us now consider the op-amp. According to
|
||||
%FMD-91~\cite{fmd91}[3-116] an op-amp may have the following failure modes:
|
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%latchup(12.5\%), latchdown(6\%), nooperation(31.3\%), lowslewrate(50\%).
|
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|
||||
|
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\subsection{Analysing the non-inverting amplifier in terms of failure modes}
|
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|
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From section~\ref{sec:opamp_fms}
|
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$$ fm(OPAMP) = \{L\_{up}, L\_{dn}, Noop, L\_slew \} $$
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||||
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|
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@ -1256,7 +1263,7 @@ could be easily detected; the failure symptom $FilterIncorrect$ may be less obs
|
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%\section{Standard Non-inverting OP AMP}
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|
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This circuit is described in the Analog Applications Journal~\cite{bubba}[p.37].
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||||
The circuit uses four 45 degree phase shifts, and an inverting amplifier to provide
|
||||
The circuit implements an oscillator using four 45 degree phase shifts, and an inverting amplifier to provide
|
||||
gain and the final 180 degrees of phase shift (making a total of 360 degrees of phase shift).
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||||
|
||||
From a fault finding perspective this circuit is less than ideal.
|
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@ -1751,6 +1758,7 @@ T%he block diagram in figure~\ref{fig
|
||||
|
||||
\clearpage
|
||||
\section{Pt100 Analysis: Double failures and MTTF statistics}
|
||||
\label{sec:Pt100}
|
||||
{
|
||||
This section
|
||||
% shows a practical example of
|
||||
@ -1794,16 +1802,16 @@ diagrams to assist the reasoning process.
|
||||
This chapter describes taking
|
||||
the failure modes of the components, analysing the circuit using FMEA
|
||||
and producing a failure mode model for the circuit as a whole.
|
||||
Thus after the analysis the Pt100 temperature sensing circuit, may be viewed
|
||||
Thus after the analysis the $Pt100$ temperature sensing circuit, may be viewed
|
||||
from an FMEA perspective as a component itself, with a set of known failure modes.
|
||||
}
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[width=400pt,bb=0 0 714 180,keepaspectratio=true]{./CH5_Examples/pt100.png}
|
||||
% pt100.jpg: 714x180 pixel, 72dpi, 25.19x6.35 cm, bb=0 0 714 180
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||||
\caption{PT100 four wire circuit}
|
||||
\label{fig:pt100}
|
||||
% Pt100.jpg: 714x180 pixel, 72dpi, 25.19x6.35 cm, bb=0 0 714 180
|
||||
\caption{Pt100 four wire circuit}
|
||||
\label{fig:Pt100}
|
||||
\end{figure}
|
||||
|
||||
|
||||
@ -1821,16 +1829,16 @@ look-up tables or a suitable polynomial expression.
|
||||
\begin{figure}[h]
|
||||
\centering
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||||
\includegraphics[width=150pt,bb=0 0 273 483,keepaspectratio=true]{./CH5_Examples/vrange.png}
|
||||
% pt100.jpg: 714x180 pixel, 72dpi, 25.19x6.35 cm, bb=0 0 714 180
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||||
\caption{PT100 expected voltage ranges}
|
||||
\label{fig:pt100vrange}
|
||||
% Pt100.jpg: 714x180 pixel, 72dpi, 25.19x6.35 cm, bb=0 0 714 180
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||||
\caption{Pt100 expected voltage ranges}
|
||||
\label{fig:Pt100vrange}
|
||||
\end{figure}
|
||||
|
||||
|
||||
The voltage ranges we expect from this three stage potential divider\footnote{
|
||||
two stages are required for validation, a third stage is used to measure the current flowing
|
||||
through the circuit to obtain accurate temperature readings}
|
||||
are shown in figure \ref{fig:pt100vrange}. Note that there is
|
||||
are shown in figure \ref{fig:Pt100vrange}. Note that there is
|
||||
an expected range for each reading, for a given temperature span.
|
||||
Note that the low reading goes down as temperature increases, and the higher reading goes up.
|
||||
For this reason the low reading will be referred to as {\em sense-}
|
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@ -1841,7 +1849,7 @@ and the higher as {\em sense+}.
|
||||
For electronic and accuracy reasons, a four wire circuit is preferred
|
||||
because of resistance in the cables. Resistance from the supply
|
||||
causes a slight voltage
|
||||
drop in the supply to the Pt100. As no significant current
|
||||
drop in the supply to the $Pt100$. As no significant current
|
||||
is carried by the two `sense' lines, the resistance back to the ADC
|
||||
causes only a negligible voltage drop, and thus the four wire
|
||||
configuration is more accurate\footnote{The increased accuracy is because the voltage measured, is the voltage across
|
||||
@ -1853,12 +1861,12 @@ The current flowing though the
|
||||
whole circuit can be measured on the PCB by reading a third
|
||||
sense voltage from one of the load resistors. Knowing the current flowing
|
||||
through the circuit
|
||||
and knowing the voltage drop over the PT100, we can calculate its
|
||||
and knowing the voltage drop over the $Pt100$, we can calculate its
|
||||
resistance by Ohms law $V=I.R$, $R=\frac{V}{I}$.
|
||||
Thus a little loss of supply current due to resistance in the cables
|
||||
does not impinge on accuracy.
|
||||
The resistance to temperature conversion is achieved
|
||||
through the published Pt100 tables\cite{eurothermtables}.
|
||||
through the published $Pt100$ tables\cite{eurothermtables}.
|
||||
The standard voltage divider equations (see figure \ref{fig:vd} and
|
||||
equation \ref{eqn:vd}) can be used to calculate
|
||||
expected voltages for failure mode and temperature reading purposes.
|
||||
@ -1879,7 +1887,7 @@ expected voltages for failure mode and temperature reading purposes.
|
||||
|
||||
\subsection{Safety case for 4 wire circuit}
|
||||
|
||||
This sub-section looks at the behaviour of the PT100 four wire circuit
|
||||
This sub-section looks at the behaviour of the $Pt100$ four wire circuit
|
||||
for the effects of component failures.
|
||||
All components have a set of known `failure modes'.
|
||||
In other words we know that a given component can fail in several distinct ways.
|
||||
@ -1895,22 +1903,22 @@ Where this occurs a circuit re-design is probably the only sensible course of ac
|
||||
|
||||
\fmodegloss
|
||||
|
||||
\paragraph{Single Fault FMEA Analysis of Pt100 Four wire circuit}
|
||||
\paragraph{Single Fault FMEA Analysis of $Pt100$ Four wire circuit}
|
||||
|
||||
\label{fmea}
|
||||
The PTt00 circuit consists of three resistors, two `current~supply'
|
||||
wires and two `sensor' wires.
|
||||
Resistors according to the European Standard EN298:2003~\cite{en298}[App.A]
|
||||
, are considered to fail by either going OPEN or SHORT circuit\footnote{EN298:2003~\cite{en298} also requires that components are downrated,
|
||||
and so in the case of resistors the parameter change failure mode~\cite{fmd-91}[2-23] can be ommitted.}.
|
||||
Resistors %according to the European Standard EN298:2003~\cite{en298}[App.A]
|
||||
, are considered to fail by either going OPEN or SHORT (see section~\ref{sec:res_fms}). %circuit\footnote{EN298:2003~\cite{en298} also requires that components are downrated,
|
||||
%and so in the case of resistors the parameter change failure mode~\cite{fmd-91}[2-23] can be ommitted.}.
|
||||
%Should wires become disconnected these will have the same effect as
|
||||
%given resistors going open.
|
||||
For the purpose of this analyis;
|
||||
$R_{1}$ is the \ohms{2k2} from 5V to the thermistor,
|
||||
$R_3$ is the PT100 thermistor and $R_{2}$ connects the thermistor to ground.
|
||||
$R_3$ is the Pt100 thermistor and $R_{2}$ connects the thermistor to ground.
|
||||
|
||||
We can define the terms `High Fault' and `Low Fault' here, with reference to figure
|
||||
\ref{fig:pt100vrange}. Should we get a reading outside the safe green zone
|
||||
\ref{fig:Pt100vrange}. Should we get a reading outside the safe green zone
|
||||
in the diagram we can consider this a fault.
|
||||
Should the reading be above its expected range this is a `High Fault'
|
||||
and if below a `Low Fault'.
|
||||
@ -1946,14 +1954,14 @@ $R_2$ SHORT & - & Low Fault & Value Out of Range Value \\
|
||||
From table \ref{ptfmea} it can be seen that any component failure in the circuit
|
||||
should cause a common symptom, that of one or more of the values being `out of range'.
|
||||
Temperature range calculations and detailed calculations
|
||||
on the effects of each test case are found in section \ref{pt100range}
|
||||
and \ref{pt100temp}.
|
||||
on the effects of each test case are found in section \ref{Pt100range}
|
||||
and \ref{Pt100temp}.
|
||||
|
||||
%\paragraph{Consideration of Resistor Tolerance}
|
||||
%
|
||||
%The separate sense lines ensure the voltage read over the PT100 thermistor are not
|
||||
%The separate sense lines ensure the voltage read over the Pt100 thermistor are not
|
||||
%altered due to having to pass any significant current.
|
||||
%The PT100 element is a precision part and will be chosen for a specified accuracy/tolerance range.
|
||||
%The Pt100 element is a precision part and will be chosen for a specified accuracy/tolerance range.
|
||||
%One or other of the load resistors (the one we measure current over) should also
|
||||
%be of this accuracy.
|
||||
%
|
||||
@ -1961,21 +1969,21 @@ and \ref{pt100temp}.
|
||||
%(typically $\leq \; 50(ppm)\Delta R \propto \Delta \oc $), and should be subjected to
|
||||
%a narrow temperature range anyway, being mounted on a PCB.
|
||||
%\glossary{{PCB}{Printed Circuit Board}}
|
||||
%To calculate the resistance of the PT100 element % (and thus derive its temperature),
|
||||
%To calculate the resistance of the Pt100 element % (and thus derive its temperature),
|
||||
%having the voltage over it, we now need the current.
|
||||
%Lets use, for the sake of example $R_2$ to measure the current flowing in the temperature sensor loop.
|
||||
%As the voltage over $R_3$ is relative (a design feature to eliminate resistance effects of the cables).
|
||||
%We can calculate the current by reading
|
||||
%the voltage over the known resistor $R2$.\footnote{To calculate the resistance of the PT100 we need the current flowing though it.
|
||||
%the voltage over the known resistor $R2$.\footnote{To calculate the resistance of the Pt100 we need the current flowing though it.
|
||||
%We can determine this via ohms law applied to $R_2$, $V=IR$, $I=\frac{V}{R_2}$,
|
||||
%and then using $I$, we can calculate $R_{3} = \frac{V_{R3}}{I}$.}
|
||||
%As these calculations are performed by ohms law, which is linear, the accuracy of the reading
|
||||
%will be determined by the accuracy of $R_2$ and $R_{3}$. It is reasonable to
|
||||
%take the mean square error of these accuracy figures.
|
||||
|
||||
\paragraph{Range and PT100 Calculations}
|
||||
\label{pt100temp}
|
||||
Pt100 resistors are designed to
|
||||
\paragraph{Range and $Pt100$ Calculations}
|
||||
\label{Pt100temp}
|
||||
$Pt100$ resistors are designed to
|
||||
have a resistance of \ohms{100} at {0\oc} \cite{aoe},\cite{eurothermtables}.
|
||||
A suitable `wider than to be expected range' was considered to be {0\oc} to {300\oc}
|
||||
for a given application.
|
||||
@ -1990,8 +1998,8 @@ As the Pt100 forms a potential divider with the \ohms{2k2} load resistors,
|
||||
the upper and lower readings can be calculated thus:
|
||||
|
||||
|
||||
$$ highreading = 5V.\frac{2k2+pt100}{2k2+2k2+pt100} $$
|
||||
$$ lowreading = 5V.\frac{2k2}{2k2+2k2+pt100} $$
|
||||
$$ highreading = 5V.\frac{2k2+Pt100}{2k2+2k2+pt100} $$
|
||||
$$ lowreading = 5V.\frac{2k2}{2k2+2k2+Pt100} $$
|
||||
So by defining an acceptable measurement/temperature range,
|
||||
and ensuring the
|
||||
values are always within these bounds, we can be confident that none of the
|
||||
@ -1999,8 +2007,8 @@ resistors in this circuit has failed.
|
||||
|
||||
To convert these to twelve bit ADC (\adctw) counts:
|
||||
|
||||
$$ highreading = 2^{12}.\frac{2k2+pt100}{2k2+2k2+pt100} $$
|
||||
$$ lowreading = 2^{12}.\frac{2k2}{2k2+2k2+pt100} $$
|
||||
$$ highreading = 2^{12}.\frac{2k2+Pt100}{2k2+2k2+pt100} $$
|
||||
$$ lowreading = 2^{12}.\frac{2k2}{2k2+2k2+Pt100} $$
|
||||
|
||||
|
||||
\begin{table}[ht]
|
||||
@ -2030,7 +2038,7 @@ will detect it.
|
||||
|
||||
\paragraph{Consideration of Resistor Tolerance.}
|
||||
%
|
||||
The separate sense lines ensure the voltage read over the Pt100 thermistor is not
|
||||
The separate sense lines ensure the voltage read over the $Pt100$ thermistor is not
|
||||
altered by to having to pass any significant current. The current is supplied
|
||||
by separate wires and the resistance in those are effectively cancelled
|
||||
out by considering the voltage reading over $R_3$ to be relative.
|
||||
@ -2058,7 +2066,7 @@ will be determined by the accuracy of $R_2$ and $R_{3}$. It is reasonable to
|
||||
take the mean square error of these accuracy figures~\cite{easp}.
|
||||
|
||||
|
||||
\paragraph{Single Fault FMEA Analysis of PT100 Four wire circuit}
|
||||
\paragraph{Single Fault FMEA Analysis of $Pt100$ Four wire circuit}
|
||||
|
||||
|
||||
\ifthenelse{\boolean{pld}}
|
||||
@ -2073,10 +2081,10 @@ and are thus enclosed by one contour each.
|
||||
\fmodegloss
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[width=400pt,bb=0 0 518 365,keepaspectratio=true]{./CH5_Examples/pt100_tc.png}
|
||||
% pt100_tc.jpg: 518x365 pixel, 72dpi, 18.27x12.88 cm, bb=0 0 518 365
|
||||
\includegraphics[width=400pt,bb=0 0 518 365,keepaspectratio=true]{./CH5_Examples/Pt100_tc.png}
|
||||
% Pt100_tc.jpg: 518x365 pixel, 72dpi, 18.27x12.88 cm, bb=0 0 518 365
|
||||
\caption{Pt100 Component Failure Modes}
|
||||
\label{fig:pt100_tc}
|
||||
\label{fig:Pt100_tc}
|
||||
\end{figure}
|
||||
} % \ifthenelse {\boolean{pld}}
|
||||
|
||||
@ -2173,38 +2181,40 @@ resistors in this circuit has failed.
|
||||
{
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[width=400pt,bb=0 0 518 365,keepaspectratio=true]{./CH5_Examples/pt100_tc_sp.png}
|
||||
% pt100_tc.jpg: 518x365 pixel, 72dpi, 18.27x12.88 cm, bb=0 0 518 365
|
||||
\caption{PT100 Component Failure Modes}
|
||||
\label{fig:pt100_tc_sp}
|
||||
\includegraphics[width=400pt,bb=0 0 518 365,keepaspectratio=true]{./CH5_Examples/Pt100_tc_sp.png}
|
||||
% Pt100_tc.jpg: 518x365 pixel, 72dpi, 18.27x12.88 cm, bb=0 0 518 365
|
||||
\caption{Pt100 Component Failure Modes}
|
||||
\label{fig:Pt100_tc_sp}
|
||||
\end{figure}
|
||||
}
|
||||
|
||||
|
||||
\subsection{Derived Component : The Pt100 Circuit}
|
||||
The Pt100 circuit can now be treated as a component in its own right, and has one failure mode,
|
||||
{\textbf OUT\_OF\_RANGE}.
|
||||
{\textbf OUT\_OF\_RANGE}. This is a single, detectable failure mode. The observability of a
|
||||
fault condition is very good with this circuit.This should not be a surprise, as the four wire $Pt100$
|
||||
has been developed for safety critical temperature measurement.
|
||||
%
|
||||
\ifthenelse{\boolean{pld}}
|
||||
{
|
||||
It can now be represnted as a PLD see figure \ref{fig:pt100_singlef}.
|
||||
It can now be represented as a PLD see figure \ref{fig:Pt100_singlef}.
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[width=100pt,bb=0 0 167 194,keepaspectratio=true]{./CH5_Examples/pt100_singlef.png}
|
||||
% pt100_singlef.jpg: 167x194 pixel, 72dpi, 5.89x6.84 cm, bb=0 0 167 194
|
||||
\caption{PT100 Circuit Failure Modes : From Single Faults Analysis}
|
||||
\label{fig:pt100_singlef}
|
||||
\includegraphics[width=100pt,bb=0 0 167 194,keepaspectratio=true]{./CH5_Examples/Pt100_singlef.png}
|
||||
% Pt100_singlef.jpg: 167x194 pixel, 72dpi, 5.89x6.84 cm, bb=0 0 167 194
|
||||
\caption{Pt100 Circuit Failure Modes : From Single Faults Analysis}
|
||||
\label{fig:Pt100_singlef}
|
||||
\end{figure}
|
||||
}
|
||||
|
||||
%From the single faults (cardinality constrained powerset of 1) analysis, we can now create
|
||||
%a new derived component, the {\empt100circuit}. This has only \{ OUT\_OF\_RANGE \}
|
||||
%a new derived component, the {\emPt100circuit}. This has only \{ OUT\_OF\_RANGE \}
|
||||
%as its single failure mode.
|
||||
|
||||
|
||||
%Interestingly we can calculate the failure statistics for this circuit now.
|
||||
%Mill 1991 gives resistor stats of ${10}^{11}$ times 6 (can we get special stats for pt100) ???
|
||||
%Mill 1991 gives resistor stats of ${10}^{11}$ times 6 (can we get special stats for Pt100) ???
|
||||
%\clearpage
|
||||
\subsection{Mean Time to Failure}
|
||||
|
||||
@ -2487,14 +2497,14 @@ $$ NoOfTestCasesToCheck = 6 + 15 - ( 1 + 1 + 1 ) = 18 $$
|
||||
|
||||
As the test case are all different and are of the correct cardinalities (6 single faults and (15-3) double)
|
||||
we can be confident that we have looked at all `double combinations' of the possible faults
|
||||
in the pt100 circuit. The next task is to investigate
|
||||
in the Pt100 circuit. The next task is to investigate
|
||||
these test cases in more detail to prove the failure mode hypothesis set out in table \ref{tab:ptfmea2}.
|
||||
|
||||
|
||||
\paragraph{Proof of Double Faults Hypothesis }
|
||||
|
||||
\paragraph{ TC 7 : Voltages $R_1$ OPEN $R_2$ OPEN }
|
||||
\label{pt100:bothfloating}
|
||||
\label{Pt100:bothfloating}
|
||||
This double fault mode produces an interesting symptom.
|
||||
Both sense lines are floating.
|
||||
We cannot know what the {\adctw} readings on them will be.
|
||||
@ -2613,7 +2623,7 @@ As a symptom $TC\_7$ could be described as $FLOATING$.
|
||||
{
|
||||
We can thus draw a PLD diagram representing the
|
||||
failure modes of this functional~group, the Pt100 circuit from the perspective of double simultaneous failures,
|
||||
in figure \ref{fig:pt100_doublef}.
|
||||
in figure \ref{fig:Pt100_doublef}.
|
||||
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
@ -2633,13 +2643,13 @@ The Pt100 circuit again, can now be treated as a component in its own right, and
|
||||
|
||||
\ifthenelse{\boolean{pld}}
|
||||
{
|
||||
It can now be represented as a PLD see figure \ref{fig:pt100_doublef}.
|
||||
It can now be represented as a PLD see figure \ref{fig:Pt100_doublef}.
|
||||
\begin{figure}[h]
|
||||
\centering
|
||||
\includegraphics[width=100pt,bb=0 0 167 194,keepaspectratio=true]{./CH5_Examples/pt100_doublef.png}
|
||||
% pt100_singlef.jpg: 167x194 pixel, 72dpi, 5.89x6.84 cm, bb=0 0 167 194
|
||||
\includegraphics[width=100pt,bb=0 0 167 194,keepaspectratio=true]{./CH5_Examples/Pt100_doublef.png}
|
||||
% Pt100_singlef.jpg: 167x194 pixel, 72dpi, 5.89x6.84 cm, bb=0 0 167 194
|
||||
\caption{Pt100 Circuit Failure Modes : From Double Faults Analysis}
|
||||
\label{fig:pt100_doublef}
|
||||
\label{fig:Pt100_doublef}
|
||||
\end{figure}
|
||||
} % \ifthenelse {\boolean{pld}}
|
||||
{
|
||||
|
@ -137,9 +137,18 @@
|
||||
YEAR = "1992"
|
||||
}
|
||||
|
||||
@BOOK{opmanage,
|
||||
AUTHOR = "Roger Schroeder",
|
||||
TITLE = "Operations Management: Contemporary Concepts and Cases ISBN: 978-0073403380",
|
||||
PUBLISHER = "McGraw-Hill",
|
||||
YEAR = "2010"
|
||||
}
|
||||
|
||||
% Safeware: System safety and Computers
|
||||
|
||||
@BOOK{safeware,
|
||||
AUTHOR = "Nancy Leveson",
|
||||
TITLE = "Safeware: System safety and Computers ISBN: 0-201-11972-2",
|
||||
TITLE = " Safeware: System safety and Computers ISBN: 0-201-11972-2",
|
||||
PUBLISHER = "Addison-Wesley",
|
||||
YEAR = "2005"
|
||||
}
|
||||
|
@ -15,13 +15,14 @@
|
||||
\setlength{\textwidth}{160mm} \setlength{\textheight}{220mm}
|
||||
\setlength{\oddsidemargin}{0mm} \setlength{\evensidemargin}{0mm}
|
||||
%
|
||||
\newcommand{\abslev}{\ensuremath{\alpha}}
|
||||
\newcommand{\oc}{\ensuremath{^{o}{C}}}
|
||||
\newcommand{\adctw}{{${\mathcal{ADC}}_{12}$}}
|
||||
\newcommand{\adcten}{{${\mathcal{ADC}}_{10}$}}
|
||||
\newcommand{\ohms}[1]{\ensuremath{#1\Omega}}
|
||||
\newcommand{\fm}{\em failure~mode}
|
||||
\newcommand{\fms}{\em failure~modes}
|
||||
\newcommand{\FG}{\ensuremath{\mathbb{G}}}
|
||||
\newcommand{\FG}{\ensuremath{{G}}}
|
||||
\newcommand{\fg}{\em functional~group}
|
||||
\newcommand{\fgs}{\em functional~groups}
|
||||
\newcommand{\dc}{\em derived~component}
|
||||
@ -35,7 +36,7 @@
|
||||
\newcommand{\pic}{\em pair-wise~intersection~chain}
|
||||
\newcommand{\wrt}{\em with~respect~to}
|
||||
\newcommand{\swf}{software~function}
|
||||
\newcommand{\abslevel}{\ensuremath{\Psi}}
|
||||
% DO NOT USE THIS ONE USE \abslev \newcommand{\abslevel}{\ensuremath{\Psi}}
|
||||
\newcommand{\fmmdgloss}{\glossary{name={FMMD},description={Failure Mode Modular De-Composition, a bottom-up methodolgy for incrementally building failure mode models, using a procedure taking functional groups of components and creating derived components representing them, and in turn using the derived components to create higher level functional groups, and so on, that are used to build a failure mode model of a SYSTEM}}}
|
||||
\newcommand{\fmodegloss}{\glossary{name={failure mode},description={The way in which a failure occurs. A component or sub-system may fail in a number of ways, and each of these is a
|
||||
failure mode of the component or sub-system}}}
|
||||
|
@ -10,33 +10,51 @@
|
||||
|
||||
\vspace{2.15in}
|
||||
|
||||
{ \bf A proposed modularisation of Failure Mode Effects Analysis.}
|
||||
{
|
||||
\bf A methodology for the modularisation of Failure Mode Effects Analysis.
|
||||
}
|
||||
|
||||
%\vbox
|
||||
%{
|
||||
%Modularising FMEA has benefits of rigor, re-usability of analysis
|
||||
%and the integration of hardware and software in failure effects modelling.
|
||||
%%}
|
||||
|
||||
%
|
||||
\rule{380pt}{1pt}
|
||||
|
||||
|
||||
\vspace{1.15in}
|
||||
|
||||
{\LARGE \bf Brighton University }
|
||||
|
||||
\vspace{0.3in}
|
||||
\rule{120pt}{1pt}
|
||||
\vspace{0.1in}
|
||||
|
||||
{\bf PhD Thesis}
|
||||
|
||||
\vspace{0.1in}
|
||||
\rule{120pt}{1pt}
|
||||
\vspace{0.3in}
|
||||
|
||||
\vspace{1.0in}
|
||||
|
||||
{\large Version 1.0 \today }
|
||||
|
||||
\vspace{0.2in}
|
||||
{\large Author : R.P. Clark - 2010 }
|
||||
{\large Author : R.P. Clark - \today }
|
||||
|
||||
\rule{380pt}{1pt}
|
||||
|
||||
\end{center}
|
||||
|
||||
\vspace{1.0in}
|
||||
\begin{verbatim}
|
||||
Robin Clark
|
||||
68 Vale Avenue,
|
||||
Brighton,
|
||||
East Sussex
|
||||
|
||||
\end{verbatim}
|
||||
%\vspace{1.0in}
|
||||
%\begin{verbatim}
|
||||
% Robin Clark
|
||||
% 68 Vale Avenue,
|
||||
% Brighton,
|
||||
% East Sussex
|
||||
%
|
||||
%\end{verbatim}
|
||||
|
||||
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user