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submission_thesis/CH5_Examples/copy.tex
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@ -838,13 +838,14 @@ We can now progress the the final stage of analysis for this amplifier, by formi
%The differences are the root causes or component failure modes that %The differences are the root causes or component failure modes that
%lead to the symptoms (i.e. the symptoms are the same but causation tree will be different). %lead to the symptoms (i.e. the symptoms are the same but causation tree will be different).
We can now express the failure modes for the {\dc} $INVAMP$ thus; We can now express the failure modes for the {\dc} $INVAMP$ thus;
$$ fm(INVAMP) = \{ {lowpass}, {high}, {low} \}.$$ %% $$ fm(INVAMP) = \{ {lowpass}, {high}, {low} \}.$$
$$ fm(INVAMP) = \{ HIGH, LOW, LOW PASS \} .$$
We can draw a DAG representing the failure mode behaviour of We can draw a DAG representing the failure mode behaviour of
this amplifier (see figure~\ref{fig:invdag1}). Note that this allows us this amplifier (see figure~\ref{fig:invdag1}). Note that this allows us
to traverse from system level, or top failure modes to base component failure modes. to traverse from system level, or top failure modes to base component failure modes.
%%%%% 12DEC 2012 UP to here in notes from AF email. %%%%% 12DEC 2012 UP to here in notes from AF email.
\clearpage
\subsection{Second Approach: Inverting OpAmp analysing with three components in one larger {\fg}} \subsection{Second Approach: Inverting OpAmp analysing with three components in one larger {\fg}}
\label{subsec:invamp2} \label{subsec:invamp2}
@ -852,7 +853,8 @@ Here we analyse the same problem without using an intermediate $PD$
derived component. We would have to do this derived component. We would have to do this
if the input voltage was not constrained to being positive. if the input voltage was not constrained to being positive.
This concern is re-visited in the differencing amplifier example in the next section. This concern is re-visited in the differencing amplifier example in the next section.
%We can view the failure mode mode produced with FMMD as a DAG
%in figure~\ref{fig:
%We can use this for a more general case, because we can examine the %We can use this for a more general case, because we can examine the
%effects on the circuit for each operational case (i.e. input +ve %effects on the circuit for each operational case (i.e. input +ve
%or input -ve), see table~\ref{tbl:invamp}. %or input -ve), see table~\ref{tbl:invamp}.
@ -896,7 +898,7 @@ This concern is re-visited in the differencing amplifier example in the next sec
\end{table} \end{table}
$$ fm(INVAMP) = \{ HIGH, LOW, LOW PASS \} $$
%Much more general. OUT OF RANGE symptom maps to many component failure modes. %Much more general. OUT OF RANGE symptom maps to many component failure modes.
@ -952,7 +954,7 @@ For the unconstrained case, we have to consider all three components as one larg
\label{sec:diffamp} \label{sec:diffamp}
\begin{figure}[h] \begin{figure}[h]
\centering \centering
\includegraphics[width=200pt]{CH5_Examples/circuit1001.png} \includegraphics[width=370pt]{CH5_Examples/circuit1001.png}
% circuit1001.png: 420x300 pixel, 72dpi, 14.82x10.58 cm, bb=0 0 420 300 % circuit1001.png: 420x300 pixel, 72dpi, 14.82x10.58 cm, bb=0 0 420 300
\caption{Circuit 1} \caption{Circuit 1}
\label{fig:circuit1} \label{fig:circuit1}
@ -966,7 +968,10 @@ ensuring that they will not
electrically load the previous stage. electrically load the previous stage.
%over-load and/or unduly influence %over-load and/or unduly influence
%the sensors or circuitry supplying the voltage signals used for measurement. %the sensors or circuitry supplying the voltage signals used for measurement.
It would be desirable to represent this circuit as a {\dc} called say $DiffAMP$. Because this differencing amplifier present high impedance to both inputs, and only uses two amplifiers,
this is a useful circuit wherever a high impedance differencing amplifier is required.
It represents a circuit that would typically be re-used in many electronic circuits.
It would therefore, be desirable to represent this circuit as a {\dc} called say $DiffAMP$.
We begin by identifying functional groups from the components in the circuit. We begin by identifying functional groups from the components in the circuit.
% WE CAN RE_USE THE NONINVAMP FROM CHAPTER 4 HERE....... % WE CAN RE_USE THE NONINVAMP FROM CHAPTER 4 HERE.......
@ -1059,10 +1064,10 @@ We begin by identifying functional groups from the components in the circuit.
% %
Looking first at the components in the signal path, we notice that we have a non-inverting Looking first at the components in the signal path, we notice that we have a non-inverting
amplifier formed by R1,R2 and IC1. In fact apart from being amplifier formed by R1,R2 and IC1. In fact, apart from being
inverted visually on the schematic, it is identical to the example inverted visually on the schematic, it is identical to the example
used in section~\ref{sec:noninvamp} (the first practical example used to demonstrate FMMD). used in section~\ref{sec:noninvamp} (the first practical example used to demonstrate FMMD).
We thus re-use this and can express the failure modes for it thus: We thus re-use the {\dc} $NI\_AMP$ and can express the failure modes for it thus:
$$ fm(NI\_AMP) = \{ AMPHigh, AMPLow, LowPass \} .$$ $$ fm(NI\_AMP) = \{ AMPHigh, AMPLow, LowPass \} .$$
% %
@ -1135,7 +1140,7 @@ $$ fm(NI\_AMP) = \{ AMPHigh, AMPLow, LowPass \} .$$
\subsection{The second Stage of the amplifier} \subsection{The second Stage of the amplifier}
The second stage of this amplifier, following the signal path, is the amplifier The second stage of this amplifier, following the signal path, is the amplifier
consisting of $R3,R4,IC2$. consisting of $R3,R4$ and $IC2$.
% %
This is in exactly the same configuration as the first amplifier, but it is being fed by the first amplifier. This is in exactly the same configuration as the first amplifier, but it is being fed by the first amplifier.
The first amplifier was grounded and received as input `+V1' (presumably The first amplifier was grounded and received as input `+V1' (presumably
@ -1193,12 +1198,11 @@ $$ fm(SEC\_AMP) = \{ AMPHigh, AMPLow, LowPass, AMPIncorrectOutput \} .$$
\pagebreak[4] \pagebreak[4]
\subsection{Finishing stage of the $DiffAmp$ Analysis} \subsection{Finishing stage of the $DiffAmp$ Analysis}
For the final stage of this we can create a functional group consisting of For the final stage we create a functional group consisting of
two derived components of the type $NI\_AMP$ and $SEC\_AMP$. two derived components of the type $NI\_AMP$ and $SEC\_AMP$.
We apply FMMD analysis to this {\fg} in table~\ref{tblampfmea}.
%
\begin{table}[h+]
\begin{table}[ht]
\caption{Difference Amplifier $DiffAMP$ : Failure Mode Effects Analysis: Single Faults} % title of Table \caption{Difference Amplifier $DiffAMP$ : Failure Mode Effects Analysis: Single Faults} % title of Table
\centering % used for centering table \centering % used for centering table
\begin{tabular}{||l|c|c|l|l||} \begin{tabular}{||l|c|c|l|l||}
@ -1220,17 +1224,15 @@ two derived components of the type $NI\_AMP$ and $SEC\_AMP$.
TC4: $SEC\_AMP$ AMPHigh & Diff amplifier high & DiffAMPHigh\\ TC4: $SEC\_AMP$ AMPHigh & Diff amplifier high & DiffAMPHigh\\
TC5: $SEC\_AMP$ AMPLow & Diff amplifier low & DiffAMPLow \\ TC5: $SEC\_AMP$ AMPLow & Diff amplifier low & DiffAMPLow \\
TC6: $SEC\_AMP$ LowPass & Diff amplifier lag/lowpass & DiffAMP\_LP \\ TC6: $SEC\_AMP$ LowPass & Diff amplifier lag/lowpass & DiffAMP\_LP \\
TC7: $SEC\_AMP$ IncorrectOutput & Output voltage & DiffAMPIncorrect \\ TC7: $SEC\_AMP$ IncorrectOutput & Output voltage is not & DiffAMPIncorrect \\
& $ \neg (V2 - V1) $ & \\ \hline & proportional to $(V2 - V1)$ & \\ \hline
\hline \hline
\end{tabular} \end{tabular}
\label{ampfmea} \label{tbl:ampfmea}
\end{table} \end{table}
%
Collecting symptoms we determine the failure modes for this circuit, %$\{DiffAMPLow, DiffAMPHigh, DiffAMP\_LP, DiffAMPIncorrect \}$. Collecting symptoms we determine the failure modes for this circuit, %$\{DiffAMPLow, DiffAMPHigh, DiffAMP\_LP, DiffAMPIncorrect \}$.
and create a derived component to represent the circuit in figure~\ref{fig:circuit1}. we create a derived component to represent the failure modes of the circuit in figure~\ref{fig:circuit1}.
$$ fm (DiffAMP) = \{DiffAMPLow, DiffAMPHigh, DiffAMP\_LP, DiffAMPIncorrect\} $$ $$ fm (DiffAMP) = \{DiffAMPLow, DiffAMPHigh, DiffAMP\_LP, DiffAMPIncorrect\} $$
@ -1261,8 +1263,10 @@ terminology is called an undetectable fault.
% %
Were this failure to have safety implications, this FMMD analysis will have revealed Were this failure to have safety implications, this FMMD analysis will have revealed
the un-observability and would likely prompt re-design of this the un-observability and would likely prompt re-design of this
circuit\footnote{A typical way to solve an un-observability such as this is circuit (a typical way to solve an un-observability such as this is
to periodically switch in test signals in place of the input signal.}. to periodically switch in test signals in place of the input signal).
%\footnote{A typical way to solve an un-observability such as this is
%to periodically switch in test signals in place of the input signal.}.
\subsection{Conclusion} \subsection{Conclusion}
@ -1278,7 +1282,8 @@ of the circuit raised in section~\ref{subsec:invamp2}.
\centering \centering
\includegraphics[width=200pt]{CH5_Examples/circuit2002.png} \includegraphics[width=200pt]{CH5_Examples/circuit2002.png}
% circuit2002.png: 575x331 pixel, 72dpi, 20.28x11.68 cm, bb=0 0 575 331 % circuit2002.png: 575x331 pixel, 72dpi, 20.28x11.68 cm, bb=0 0 575 331
\caption{circuit 2} \caption{Five Pole Low Pass Filter, using two Sallen~Key stages and three op-amps.
An example of FMMD applied to a multi-stage but linear signal path topology. }
\label{fig:circuit2} \label{fig:circuit2}
\end{figure} \end{figure}
@ -1547,8 +1552,9 @@ We represent the desired FMMD hierarchy in figure~\ref{fig:circuit2h}.
\label{tbl:fivepole} \label{tbl:fivepole}
\end{table} \end{table}
We now can create a {\dc} to represent the circuit in figure~\ref{fig:circuit2}, we can call it We now can create a {\dc} to represent the circuit in figure~\ref{fig:circuit2}, we call this
$FivePoleLP$ and applying the $fm$ function to it (see table~\ref{tbl:fivepole}) yields $fm(FivePoleLP) = \{ HIGH, LOW, FilterIncorrect, NO\_SIGNAL \}$. $FivePoleLP$: applying the $fm$ function (see table~\ref{tbl:fivepole})
yields $fm(FivePoleLP) = \{ HIGH, LOW, FilterIncorrect, NO\_SIGNAL \}$.
%\pagebreak[4] %\pagebreak[4]
@ -1585,7 +1591,7 @@ The circuit implements an oscillator using four 45 degree phase shifts, and an i
gain and the final 180 degrees of phase shift (making a total of 360). % degrees of phase shift). gain and the final 180 degrees of phase shift (making a total of 360). % degrees of phase shift).
The circuit provides two outputs with a quadrature phase relationship. The circuit provides two outputs with a quadrature phase relationship.
% %
From a fault finding perspective this circuit cannot be de-composed From a fault finding perspective this circuit cannot be decomposed
because the whole circuit is enclosed within a feedback loop, because the whole circuit is enclosed within a feedback loop,
hence a fault anywhere in the loop is likely to affect all stages. hence a fault anywhere in the loop is likely to affect all stages.
% %
@ -1630,7 +1636,7 @@ $$ fm(INVAMP) = \{ AMP\_High, AMP\_Low, LowPass \}. $$ % \{ HIGH, LOW, LOW PASS
This consists of a resistor and a capacitor. We already have failure mode models for these components -- $ fm(R) = \{OPEN, SHORT\}$, $fm(C) = \{OPEN, SHORT\}$ -- This consists of a resistor and a capacitor. We already have failure mode models for these components -- $ fm(R) = \{OPEN, SHORT\}$, $fm(C) = \{OPEN, SHORT\}$ --
we now need to see how these failure modes would affect the phase shifter. Note that the circuit here we now need to see how these failure modes would affect the phase shifter. Note that the circuit here
is identical to the low pass filter in circuit topology (see \ref{sec:lp}), but its intended use is different. is identical to the low pass filter in circuit topology (see section~\ref{sec:lp}), but its intended use is different.
We have to analyse this circuit from the perspective of it being a {\em phase~shifter} not a {\em low~pass~filter}. We have to analyse this circuit from the perspective of it being a {\em phase~shifter} not a {\em low~pass~filter}.
Our functional group for the phase shifter consists of a resistor and a capacitor, $G_0 = \{ R, C \}$ Our functional group for the phase shifter consists of a resistor and a capacitor, $G_0 = \{ R, C \}$
(FMMD analysis details at section~\ref{detail:PHS45}) (FMMD analysis details at section~\ref{detail:PHS45})
@ -1643,14 +1649,15 @@ $$ fm (G_0) = \{ nosignal, 0\_phaseshift \} $$
%23SEP2012 %23SEP2012
\subsection{Non Inverting Buffer: NIBUFF.} \subsection{Non Inverting Buffer: NIBUFF.}
The non-inverting buffer functional group, is comprised of one component, an op-amp. The non-inverting buffer {\fg}, is comprised of one component, an op-amp.
We use the failure modes for an op-amp~\cite{fmd91}[p.3-116] to represent this group. We use the failure modes for an op-amp~\cite{fmd91}[p.3-116] to represent this group.
% GARK % GARK
$$ fm(NIBUFF) = fm(OPAMP) = \{L\_{up}, L\_{dn}, Noop, L\_slew \} $$ We can express the failure modes for the ono-inverting buffer ($NIBUFF$) thus:
$$ fm(NIBUFF) = fm(OPAMP) = \{L\_{up}, L\_{dn}, Noop, L\_slew \} . $$
Because we obtain the failure modes for $NIBUFF$ from the literature, %Because we obtain the failure modes for $NIBUFF$ from the literature,
its comparison complexity is zero. In re-using {\dcs} we expend no extra analysis effort. %its comparison complexity is zero. In re-using {\dcs} we expend no extra analysis effort.
$$ CC(NIBUFF) = 0 $$ %$$ CC(NIBUFF) = 0 $$
%\subsection{Forming a functional group from the PHS45 and NIBUFF.} %\subsection{Forming a functional group from the PHS45 and NIBUFF.}
% describe what we are doing, a buffered 45 degree phase shift element % describe what we are doing, a buffered 45 degree phase shift element
@ -1666,7 +1673,7 @@ Initially we use the first identified {\fgs} to create our model without further
\subsection{FMMD Analysis using initially identified functional groups} \subsection{FMMD Analysis using initially identified functional groups}
Our functional group for this analysis can be expressed thus: Our {\fg} for this analysis can be expressed thus:
% %
%$$ G^1_0 = \{ PHS45^1_1, NIBUFF^0_1, PHS45^1_2, NIBUFF^0_2, PHS45^1_3, NIBUFF^0_3 PHS45^1_4, INVAMP^1_0 \} ,$$ %$$ G^1_0 = \{ PHS45^1_1, NIBUFF^0_1, PHS45^1_2, NIBUFF^0_2, PHS45^1_3, NIBUFF^0_3 PHS45^1_4, INVAMP^1_0 \} ,$$
$$ G = \{ PHS45, NIBUFF, PHS45, NIBUFF, PHS45, NIBUFF PHS45, INVAMP \} ,$$ $$ G = \{ PHS45, NIBUFF, PHS45, NIBUFF, PHS45, NIBUFF PHS45, INVAMP \} ,$$
@ -1768,7 +1775,7 @@ providing an amplified $225^{\circ}$ phase shift, analysed in table~\ref{tbl:phs
resulting in the {\dc} $PHS225AMP$. resulting in the {\dc} $PHS225AMP$.
% %
%---with the remaining $PHS45$ and the $INVAMP$ (re-used from section~\ref{sec:invamp})in a second group $PHS225AMP$--- %---with the remaining $PHS45$ and the $INVAMP$ (re-used from section~\ref{sec:invamp})in a second group $PHS225AMP$---
Finally we form a final {\fg} with $PHS135BUFFERED$ and $PHS225AMP$, Finally we form a final {\fg} with $PHS135BUFFERED$ and $PHS225AMP$.
%in a final stage (see figure~{fig:bubbaeuler2}) % \ref{fig:poss2finalbubba}) %in a final stage (see figure~{fig:bubbaeuler2}) % \ref{fig:poss2finalbubba})
% %
%We can take a more modular approach by creating two intermediate functional groups, a buffered $45^{\circ}$ phase shifter (BUFF45) %We can take a more modular approach by creating two intermediate functional groups, a buffered $45^{\circ}$ phase shifter (BUFF45)
@ -1784,16 +1791,17 @@ Finally we form a final {\fg} with $PHS135BUFFERED$ and $PHS225AMP$,
% %
% %
% %
We analyse the {\fg} (see section~\ref{detail:BUFF45}) and create a derived component, $BUFF45$ which has the following failure modes: We analyse this {\fg} (see section~\ref{detail:BUFF45}) and create a derived component, $BUFF45$ which has the following failure modes:
$$ $$
fm (BUFF45) = \{ 0\_phaseshift, NO\_signal .\} % 90\_phaseshift, fm (BUFF45) = \{ 0\_phaseshift, NO\_signal \} .% 90\_phaseshift,
$$ $$
% %
%$$ CC(BUFF45) = 7 \times 1 = 7 $$ %$$ CC(BUFF45) = 7 \times 1 = 7 $$
% %
We can now combine three $BUFF45$ {\dcs} and create a $PHS135BUFFERED$ {\dc}. Three $BUFF45$ {\dcs} form a {\fg}, and after FMMD analysis
we create a $PHS135BUFFERED$ {\dc}. The FMMD analysis may be viewed at section~\ref{detail:PHS135BUFFERED}. %
%
% %
% %
%$$ CC (PHS135BUFFERED) = 3 \times 2 = 6 $$ %$$ CC (PHS135BUFFERED) = 3 \times 2 = 6 $$
% %
@ -1844,9 +1852,12 @@ to analyse in the future.
% %
%In general with large functional groups the comparison complexity %In general with large functional groups the comparison complexity
%is higher, by an order of $O(N^2)$. %is higher, by an order of $O(N^2)$.
Smaller functional groups mean less by-hand checks are required. Smaller functional groups signify less by-hand checks and
It also means a more finely grained model. This means that a more finely grained model.
there are more {\dcs} and therefore increases the potential for re-use of pre-analysed {\dcs}. This means that
there would be more {\dcs} and therefore increases the potential for re-use of pre-analysed {\dcs}.
A finer grained model---with potentially more hierarchy stages---conveys that more
work, or reasoning has been used in the analysis.
% HTR The more we can modularise, the more we decimate the $O(N^2)$ effect % HTR The more we can modularise, the more we decimate the $O(N^2)$ effect
% HTR of complexity comparison. % HTR of complexity comparison.
% %
@ -1918,8 +1929,7 @@ and fed to the D type flip flop.
% %
The output of the flip flop is routed to the digital output and to the feedback loop. The output of the flip flop is routed to the digital output and to the feedback loop.
It must be level converted, i.e. from digital logic voltage levels to analogue levels, before being fed to the analogue feedback. It must be level converted, i.e. from digital logic voltage levels to analogue levels, before being fed to the analogue feedback.
It is level converted to an analogue signal by IC3. It is level converted to an analogue signal by IC3---i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage---
(i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage)
and fed into the summing integrator completing the negative feedback loop. and fed into the summing integrator completing the negative feedback loop.
% %
In essence this implements an over-sampling one bit analogue to digital converter~\cite{ehb}[pp.729-730]. In essence this implements an over-sampling one bit analogue to digital converter~\cite{ehb}[pp.729-730].
@ -1945,21 +1955,23 @@ and obtain its failure modes, which we can express using the $fm$ function:
%% %%
$$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$ $$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$
% %
The resistors and capacitor failure modes we take from EN298~\cite{en298}[An.A] The resistors and capacitor failure modes we take from EN298~\cite{en298}[An.A].
We express the failure modes for the resistors (R) and Capacitors (C) thus:
% %
$$ fm ( R ) = \{OPEN, SHORT\} $$ $$ fm ( R ) = \{OPEN, SHORT\},$$
% %
$$ fm ( C ) = \{OPEN, SHORT\} $$ $$ fm ( C ) = \{OPEN, SHORT\}. $$
% %
We are also given a CLOCK. For the purpose of example we shall attribute We are also given a CLOCK. For the purpose of example we shall attribute
one failure mode to this, that it might stop. one failure mode to this, that it might stop.
We express the failure modes of the CLOCK, thus:
% %
$$ fm ( CLOCK ) = \{ STOPPED \} $$ $$ fm ( CLOCK ) = \{ STOPPED \}. $$
\subsection{Identifying initial {\fgs}} \subsection{Identifying initial {\fgs}}
\subsubsection{Summing Junction Integrator (SUMJINT)} \subsubsection{Summing Junction Integrator (SUMJINT)}
We now need to choose {\fgs}. The most obvious way to find initial {\fgs} is We next choose {\fgs}. The most obvious way to find initial {\fgs} is
to follow the signal path. The signal path is circular, but we can start to follow the signal path. The signal path is circular, but we can start
with the input voltage, which is applied via $R2$, we term this voltage $V_{in}$. with the input voltage, which is applied via $R2$, we term this voltage $V_{in}$.
% %
@ -1977,7 +1989,7 @@ $$FG = \{R1, R2, IC1, C1 \}$$
That is the failure modes (see FMMD analysis at~\ref{detail:SUMJINT})of our new {\dc} That is the failure modes (see FMMD analysis at~\ref{detail:SUMJINT})of our new {\dc}
$SUMJINT$ are $$\{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$ $SUMJINT$ are $$\{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$
\clearpage %\clearpage
\subsubsection{High Impedance Signal Buffer (HISB)} \subsubsection{High Impedance Signal Buffer (HISB)}
@ -2015,7 +2027,7 @@ fm(PD) = \{ HIGH, LOW \}.
$$ $$
% %
IC3 is an op-amp and has the failure modes IC3 is an op-amp and has the failure modes
$$fm(IC3) = \{\{ HIGH, LOW, NOOP, LOW\_SLEW \} . $$ $$fm(IC3) = \{ HIGH, LOW, NOOP, LOW\_SLEW \} . $$
% %
The digital signal is supplied to the non-inverting input. The digital signal is supplied to the non-inverting input.
The output is a voltage level in the analogue domain $-V$ or $+V$. The output is a voltage level in the analogue domain $-V$ or $+V$.
@ -2099,7 +2111,7 @@ and make a complete failure mode for the {\sd}.
% \end{figure} % \end{figure}
\clearpage %\clearpage
@ -2109,13 +2121,12 @@ We now form a {\fg} with the two derived components $HISB$ and $SUMJINT$.
This forms a buffered integrating summing junction. We analyse this using FMMD This forms a buffered integrating summing junction. We analyse this using FMMD
(see section~\ref{detail:BISJ}). (see section~\ref{detail:BISJ}).
%which we analyse in table~\ref{tbl:BISJ}. %which we analyse in table~\ref{tbl:BISJ}.
We define this {\fg} thus:
$$ FG = \{ HISB, SUMJINT \} $$ $ FG = \{ HISB, SUMJINT \} .$
%
Using the $fm$ function we define the failure modes of
Our derived component BISJ has the failure mode defined by the $fm$ function thus: our derived component BISJ thus:
%
$$ fm(BISJ) = \{ OUTPUT STUCK , REDUCED\_INTEGRATION \} . $$ $$ fm(BISJ) = \{ OUTPUT STUCK , REDUCED\_INTEGRATION \} . $$