diff --git a/submission_thesis/CH4_FMMD/copy.tex b/submission_thesis/CH4_FMMD/copy.tex index b67981a..663bc70 100644 --- a/submission_thesis/CH4_FMMD/copy.tex +++ b/submission_thesis/CH4_FMMD/copy.tex @@ -149,7 +149,7 @@ and determine how they affect the operation of the potential divider. For this example we look at single failure modes only. For each failure mode in our {\fg} `potential~divider' -we can assign a {\fc} number (see table \ref{pdfmea}). +we can assign a {\fc} number (see table \ref{tbl:pdfmea}). Each {\fc} is analysed to determine the `symptom' of the potential dividers' operation. For instance if resistor $R_1$ was to go open, then the circuit would not be grounded and the @@ -175,7 +175,7 @@ gives a high voltage output.%We can now consider the {\fg} FS4: $R_2$ OPEN & LOW & LowPD \\ \hline \hline \end{tabular} -\label{pdfmea} +\label{tbl:pdfmea} \end{table} } diff --git a/submission_thesis/CH5_Examples/Makefile b/submission_thesis/CH5_Examples/Makefile index db75384..5b89d49 100644 --- a/submission_thesis/CH5_Examples/Makefile +++ b/submission_thesis/CH5_Examples/Makefile @@ -5,7 +5,7 @@ PNG_DIA = blockdiagramcircuit2.png bubba_oscillator_block_diagram.png circuit1 poss1finalbubba.png poss2finalbubba.png pt100.png pt100_doublef.png pt100_singlef.png \ pt100_tc.png pt100_tc_sp.png shared_component.png stat_single.png three_tree.png \ tree_abstraction_levels.png vrange.png sigma_delta_block.png ftcontext.png ct1.png hd.png \ - sigdel1.png + sigdel1.png sdadc.png diff --git a/submission_thesis/CH5_Examples/copy.tex b/submission_thesis/CH5_Examples/copy.tex index 675a3b9..eabe914 100644 --- a/submission_thesis/CH5_Examples/copy.tex +++ b/submission_thesis/CH5_Examples/copy.tex @@ -1656,9 +1656,9 @@ The more we can modularise, the more we decimate the $O(N^2)$ effect of complexity comparison. -\section{Sigma Delta Analogue to Digital Converter ($\Sigma \Delta $ADC)} +\section{Sigma Delta Analogue to Digital Converter.} %($\Sigma \Delta ADC$)} -The following example shows the analysis of a mixed analogue and digital circuit. +The following example is used to demonstrate FMMD analysis of a mixed analogue and digital circuit (see figure~\ref{fig:sigmadelta}). \begin{figure}[h] \centering \includegraphics[width=200pt]{./CH5_Examples/circuit4004.png} @@ -1684,7 +1684,7 @@ The following example shows the analysis of a mixed analogue and digital circuit \paragraph{How the circuit works.} The diagram in~\ref{fig:sigmadeltablock} shows the signal path used -by this configuration for a $\Sigma \Delta $ADC. +by this configuration for a \sd. % It works by placing the analogue voltage to be read into a mixed analogue and digital feedback circuit. @@ -1695,16 +1695,16 @@ signal with the input. The output of the integrator is digitally cleaned-up by IC2 (i.e. output is TRUE or FALSE for digital logic) which acts as a comparator, and fed to the D type flip flop. % -The output of the flip flop is a digital representation +The output of the flip flop forms a bit pattern representing the value of the input voltage. % -The output of the flip flop, is now cleaned as an analogue signal +The output of the flip flop, is now level converted to an analogue signal (i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage) and fed into the summing integrator completing the negative feedback loop. -\subsection{FMMD analysis of $\Sigma \Delta $ADC} +\subsection{FMMD analysis of \sd } -The partslist for the $\Sigma \Delta $ADC +The partslist for the \sd : $$\{ IC1, IC2, IC3, IC4, R1, R2, R3, R4, C1 \} $$. @@ -1729,12 +1729,15 @@ $$ fm ( C ) = \{OPEN, SHORT\} $$ \subsubsection{Summing Junction} We now need to choose {\fgs}. The signal path is circular, but we can start -with the input voltage, which is applied to $R2$, we can term this voltage $V_{in}$. -$R2$ and $R1$ form a summing junction to IC1. -$R1$ supplies the feedback voltage for the ADC, we can term this voltage as $V_{fb}$ -This can be our first {\fg}. For the symptoms, we have to think in terms of the effect -on its performance as a summing junction and not be -distracted by the integrator formed by $C_1$ and $IC1$. +with the input voltage, which is applied via $R2$, we term this voltage $V_{in}$. +% +The feedback voltage for the ADC is supplied via $R1$, we term this voltage as $V_{fb}$. +%The input voltage is supplied via $R2$ and we term this voltage as $V_{in}$. +$R2$ and $R1$ form a summing junction to IC1: they thus work to fulfil this specific function. +This can be our first {\fg} and we analyse it in table~\ref{tbl:suml=j}. +%For the symptoms, we have to think in terms of the effect +%on its performance as a summing junction and not be +%distracted by the integrator formed by $C_1$ and $IC1$. $$G^0_1 = \{R1, R2 \}$$ @@ -1757,17 +1760,19 @@ $$G^0_1 = \{R1, R2 \}$$ \end{table} -From the analysis in table~\ref{tbl:sumj}, we can now create a derived component -$SUMJ$ which has the failure modes from collecting its symptoms. -We can state +From the analysis in table~\ref{tbl:sumj} we collect symptoms. +We can create the derived component +$SUMJ$.% which has the failure modes from collecting its symptoms. +We now state: -$$ fm(SUMJ) = \{ V_{in} DOM, V_{fb} DOM \} $$ +$$ fm(SUMJ) = \{ V_{in} DOM, V_{fb} DOM \} .$$ \subsubsection{Buffered Integrator} Following the signal path, the next functional group is the integrator. -This integrator is formed by $C$ by $IC2$\cite{aoe}[ch.4]. -The output of the integrator is fed into IC2, which acts as a buffer. +% +This integrator is formed by placing $C1$ in the negative feedback loop of $IC2$\cite{aoe}[p.222]. +The output of the integrator is fed into IC2, which acts as a buffer, %performing the function of isolating the integrator from any load on its output. These three components work together to form a buffered integrator, @@ -1822,7 +1827,7 @@ The potential divider provides a mid rail reference voltage to the inverting input of IC3. \paragraph{Potential divider Formed by R3,R4.} -We re-use the analysis from section~\ref{sec:pd}, and used the derived component $PD$ +We re-use the analysis from table~\ref{tbl:pdfmea}, and used the derived component $PD$ to represent the potential divider formed by R3 and R4. Because PD is a derived component, we can denote this by super-scripting it with its abstraction level of 1, thus $PD^1$. $$ @@ -1840,6 +1845,7 @@ We now form a {\fg} from $PD^1$ and $IC3$. $$ G^1_0 = \{ PD^1, IC3 \} $$ We now analyse the {\fg} $G^1$ in table~\ref{tbl:DS2AS}. +%$$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ \begin{table}[h+] \caption{$PD^1, IC3$ Digital level to analogue level converter: Failure Mode Effects Analysis} % title of Table @@ -1898,19 +1904,139 @@ IC4 is as yet unused, the signal path connects IC4 and DL2AL. These seem natural for the next {\fg}. BFINT and SUMJ are adjacent in the signal path and these are chosen as a {\fg} as well. +\clearpage -\subsubsection{{\fg} BFINT and SUMJ} -\subsubsection{{\fg} IC4 and DL2AL} + + +\subsubsection{{\fg} $BFINT^1$ and $SUMJ^1$} + +We now form a {\fg} with the two derived components $BFINT^1$ and $SUMJ^1$. +This forms a buffered integrating summing junction which we analyse in table~\ref{tbl:BISJ}. + +$$ G^1_0 = \{ BFINT^1, SUMJ^1 \} $$ + +%$$ fm (BFINT) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ +%$$ fm(SUMJ) = \{ V_{in} DOM, V_{fb} DOM \} .$$ + +\begin{table}[h+] +\caption{ $BFINT^1, SUMJ^1$ buffered integrating summing junction: Failure Mode Effects Analysis} % title of Table +\label{tbl:DS2AS} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + & & & & \\ + \hline \hline + FS1: $SUMJ^1$ $V_{in} DOM$ & & output integral of $V_{in}$ & & $OUTPUT STUCK$ \\ + FS2: $SUMJ^1$ $V_{fb} DOM$ & & output integral of $V_{fb}$ & & $OUTPUT STUCK$ \\ \hline + +%\hline + FS3: $BFINT^1$ $HIGH$ & & output perm. high & & $OUTPUT STUCK$ \\ + FS4: $BFINT^1$ $LOW$ & & output perm. low & & $OUTPUT STUCK$ \\ \hline + FS5: $BFINT^1$ $ NO\_INTEGRATION$ & & no current drive & & $OUTPUT STUCK$ \\ + FS6: $BFINT^1$ $LOW\_SLEW$ & & delayed signal & & $REDUCED\_INTEGRATION$ \\ \hline +\hline + +\end{tabular} +\end{table} + + + +We now collect symptoms $\{ OUTPUT STUCK , REDUCED\_INTEGRATION \}$, and create a {\dc} +called $BISJ^2$. + + + + + + + + + + +\subsubsection{{\fg} $IC4$ and $DL2AL$} + +%$$ fm (DL2AL^2) = \{ LOW, HIGH, LOW\_SLEW \} $$ +%$$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$ + +The functional group formed by $IC4$ and $DL2AL$ takes the flip flop clocked and buffered +value, and outputs it at analogue voltage levels for the summing junction. + +$ G^2_1 = \{ IC4^0, DL2AL^2 \} $ + +We analyse the buffered flip flop circuitry in table~\ref{tbl:FFB}. + +\begin{table}[h+] +\caption{ $IC4^0,DL2AL^2$ flip flop buffered: Failure Mode Effects Analysis} % title of Table +\label{tbl:FFB} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + & & & & \\ + \hline \hline + FS1: $IC4^0$ $HIGH$ & & output stuck high & & $OUTPUT STUCK$ \\ + FS2: $IC4^0$ $LOW$ & & output stuck low & & $OUTPUT STUCK$ \\ + FS3: $IC4^0$ $NOOP$ & & output stuck low & & $OUTPUT STUCK$ \\ \hline +%\hline + FS4: $DL2AL^2$ $LOW$ & & output perm. high & & $OUTPUT STUCK$ \\ + FS5: $DL2AL^2$ $HIGH$ & & output perm. low & & $OUTPUT STUCK$ \\ \hline + FS6: $DL2AL^2$ $LOW\_SLEW$ & & no current drive & & $LOW\_SLEW$ \\ + +\hline + +\end{tabular} +\end{table} + +We now collect symptoms $\{OUTPUT STUCK, LOW\_SLEW\}$ and create a {\dc} at the third level of symptom abstraction +called $FFB^3$. \subsection{Final, top level {\fg} for sigma delta Converter} +We now have two {\dcs}, $FFB^3$ and $BISJ^2$: we form a final functional group with these: +$$ G^3_0 = \{ FFB^3, BISJ^2 \} .$$ +We analyse the buffered {\sd} circuit in table~\ref{tbl:FFB}. +% +% FFB^3 $\{OUTPUT STUCK, LOW\_SLEW\}$ +% BISJ^2 $\{ OUTPUT STUCK , REDUCED\_INTEGRATION \}$ +% +\begin{table}[h+] +\caption{ $FFB^3, BISJ^2$ \sd : Failure Mode Effects Analysis} % title of Table +\label{tbl:sd} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + & & & & \\ + \hline \hline + FS1: $FFB^3$ $OUTPUT STUCK$ & & value max high or low & & $OUTPUT\_OUT\_OF\_RANGE$ \\ + FS2: $FFB^3$ $LOW\_SLEW$ & & values will appear larger & & $OUTPUT\_INCORRECT$ \\ +% FS3: $IC4^0$ $NOOP$ & & output stuck low & & $OUTPUT STUCK$ \\ \hline +%\hline + FS3: $BISJ^2$ $OUTPUT STUCK$ & & value max high or low & & $OUTPUT\_OUT\_OF\_RANGE$ \\ + FS4: $BISJ^2$ $REDUCED\_INTEGRATION$ & & values will appear larger & & $OUTPUT\_INCORRECT$ \\ \hline + + +\hline + +\end{tabular} +\end{table} +%\clearpage +We now collect the symptoms for the \sd $ \; +\{OUTPUT\_OUT\_OF\_RANGE, OUTPUT\_INCORRECT\}$. +We can now create a {\dc} to represent the analogue to digital converter, $SADC^4$. +$$fm(SADC^4) = \{OUTPUT\_OUT\_OF\_RANGE, OUTPUT\_INCORRECT\}$$ +We now show the final hierarchy in figure~\ref{fig:sdadc}. +\begin{figure}[h] + \centering + \includegraphics[width=400pt]{./CH5_Examples/sdadc.png} + % sdadc.png: 886x1134 pixel, 72dpi, 31.26x40.01 cm, bb=0 0 886 1134 + \caption{FMMD Analysis hierarchy for the {\sd}} + \label{fig:sdadc} +\end{figure} - - +\clearpage % ] % into % @@ -1963,11 +2089,11 @@ BFINT and SUMJ are adjacent in the signal path and these are chosen as a {\fg} a % $$fm(SUMJUNCT) = \{ R1\_IN\_DOM, R2\_IN\_DOM \} $$. -The D type flip flop +%The D type flip flop %\subsection{FMMD Process applied to $\Sigma \Delta $ADC}. -T%he block diagram in figure~\ref{fig +%T%he block diagram in figure~\ref{fig \clearpage @@ -1983,8 +2109,8 @@ This section % These failure symptoms are used to define % a derived component. % -demonstrates FMMDs ability to model multiple {\fms}, and shows - how statistics for part {\fms} can be used to determine the statistical likelihood of failure symptoms. +demonstrates FMMDs ability to model multiple simultaneous {\fms}, and shows +how statistics for part {\fms} can be used to determine the statistical likelihood of failure symptoms. For this example we look at an industry standard temperature measurement circuit, diff --git a/submission_thesis/CH5_Examples/sdadc.dia b/submission_thesis/CH5_Examples/sdadc.dia new file mode 100644 index 0000000..7ff4c6b Binary files /dev/null and b/submission_thesis/CH5_Examples/sdadc.dia differ diff --git a/submission_thesis/CH5_Examples/sigdel1.dia b/submission_thesis/CH5_Examples/sigdel1.dia index fc67b8e..9e5baf7 100644 Binary files a/submission_thesis/CH5_Examples/sigdel1.dia and b/submission_thesis/CH5_Examples/sigdel1.dia differ diff --git a/submission_thesis/style.tex b/submission_thesis/style.tex index 0b1f92e..0ddc53e 100644 --- a/submission_thesis/style.tex +++ b/submission_thesis/style.tex @@ -28,7 +28,10 @@ \setlength{\oddsidemargin}{0mm} \setlength{\evensidemargin}{0mm} % \newcommand{\permil}{\ensuremath{0/{\!}_{00}}} -\newcommand{\emp}{} %% do nothing, all the italics are unnecessary +%\newcommand{\emp}{ELECTRO MAGNETIC FUKING PULSE} +\newcommand{\emp}{} %% was italics +%\newcommand{\sd}{\ensuremath{\Sigma \Delta ADC}} +\newcommand{\sd}{\ensuremath{Sigma\;Delta\;ADC}} \newcommand{\derivec}{{D}} \newcommand{\abslev}{\ensuremath{\alpha}} \newcommand{\oc}{\ensuremath{^{o}{C}}}