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Used jpg instead of eps. going over to pdflatex.

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logic_diagram/CVS/Entries
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/fmmd_hierarchy_cimg5040.eps/1.1/Sun Jul 13 17:13:12 2008//
/ldand.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldand.eps/1.1/Sun Jul 13 17:13:14 2008//
/lddc.dia/1.1/Sun Jul 13 17:13:14 2008//
/lddc.eps/1.1/Sun Jul 13 17:13:14 2008//
/ldimp.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldimp.eps/1.1/Sun Jul 13 17:13:14 2008//
/ldmeq.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldmeq.eps/1.1/Sun Jul 13 17:13:14 2008//
/ldmeq2.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldmeq2.eps/1.1/Sun Jul 13 17:13:14 2008//
/ldneg.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldneg.eps/1.1/Sun Jul 13 17:13:14 2008//
/ldor.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldor.eps/1.1/Sun Jul 13 17:13:14 2008//
/ldxor.dia/1.1/Sun Jul 13 17:13:14 2008//
/ldxor.eps/1.1/Sun Jul 13 17:13:14 2008//
/Makefile/1.2/Wed Nov 25 17:14:59 2009//
/paper.tex/1.4/Sat Nov 28 20:05:52 2009//
/inhibit.eps/1.1/Fri Jan 1 14:11:12 2010//
/inhibit.fig/1.1/Fri Jan 1 14:11:03 2010//
/repeated.eps/1.1/Fri Jan 1 14:20:31 2010//
/repeated.fig/1.1/Fri Jan 1 14:20:23 2010//
/logic_diagram.tex/1.17/Wed Jan 6 13:41:32 2010//
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fmd_docs/phd_docs/logic_diagram

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robin@192.168.2.44:/export/home/cvs/

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logic_diagram/logic_diagram.log
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126
logic_diagram/logic_diagram.tex
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@ -1,7 +1,4 @@
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.17 2010/01/06 13:41:32 robin Exp $
\end{verbatim}
\begin{abstract}
%This chapter describes using diagrams to represent propositional logic.
@ -73,7 +70,7 @@ in a text editor or spreadsheet, a visual method is percieved as being more intu
%these points may be joined.
PLDs use three visual features that
can be combined to represent logic equations. Closed contours (using dashed lines), test cases, and lines that
can be combined to represent logic equations. Closed contours, test cases, and lines that
link test cases.
All features may be labelled, and the labels must be unique within a diagram, however contours may be repeated in the diagram.
%Aditionally a label begining with the `$\neg$' character, applied only to a contour, represents negation.
@ -377,18 +374,24 @@ Joining lines thus represent dis-junction in a PLD.
\subsection{ Logical AND example }
\begin{figure}[h+]
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldand.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.6]{ldand.eps}
\caption{Logical AND}
\label{fig:ld_and}
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 279 247]{logic_diagram/ldand.jpg}
% ldand.jpg: 279x247 pixel, 72dpi, 9.84x8.71 cm, bb=0 0 279 247
\label{fig:ld_and}
\end{figure}
% \begin{figure}[h+]
% \begin{center}
% \includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldand.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
%
% %\includegraphics[scale=0.6]{ldand.eps}
% \caption{Logical AND}
% \label{fig:ld_and}
% \end{figure}
In the diagram \ref{fig:ld_and} the area of intersection between the contours $a$ and $b$
represents the conjunction of those conditions. The point $P$ represents the logic equation
@ -401,18 +404,24 @@ The proposition $P$ considers the scenario where both failure~modes are active.
\clearpage
\subsection { Logical OR example }
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 476 264]{logic_diagram/ldor.jpg}
% ldor.jpg: 476x264 pixel, 72dpi, 16.79x9.31 cm, bb=0 0 476 264
\label{fig:ld_or}
\end{figure}
\begin{figure}[h+]
%\centering
%\input{ldor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldor.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.60]{ldor.eps}
\caption{Logical OR}
\label{fig:ld_or}
\end{figure} % OR
% \begin{figure}[h+]
% %\centering
% %\input{ldor.tex}
% \begin{center}
% \includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldor.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
% %\includegraphics[scale=0.60]{ldor.eps}
% \caption{Logical OR}
% \label{fig:ld_or}
% \end{figure} % OR
The diagram \ref{fig:ld_or} is converted to Boolean logic by first looking at the test cases, and
@ -439,21 +448,26 @@ Therefore only test cases not linked by any disjunctive joining lines need be na
The diagram \ref{fig:ld_meq} can therefore be represented as in diagram \ref{fig:ld_meq2}, with
two unnamed test cases.
\begin{figure}[h+]
%\centering
%\input{millivolt_sensor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{logic_diagram/ldmeq2.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.4]{ldmeq2.eps}
\caption{Several Logical Expressions with unamed test cases}
\label{fig:ld_meq2}
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 572 297,scale=0.7,keepaspectratio=true]{logic_diagram/ldmeq2.jpg}
% ldmeq2.jpg: 572x297 pixel, 72dpi, 20.18x10.48 cm, bb=0 0 572 297
\label{fig:ld_meq2}
\end{figure}
%
% \begin{figure}[h+]
% %\centering
% %\input{millivolt_sensor.tex}
% \begin{center}
% \includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{logic_diagram/ldmeq2.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
% %\includegraphics[scale=0.4]{ldmeq2.eps}
% \caption{Several Logical Expressions with unamed test cases}
% \label{fig:ld_meq2}
% \end{figure}
\paragraph{How this would be interpreted in failure analysis}
In failure analysis, this could be considered to be a sub-system with two failure states $a$ and $b$.
@ -473,13 +487,23 @@ of $a$ and $b$ both being active is not defined on this diagram.
Repeated contours are allowed in PLD diagrams.
Logical contradictions or tautologies can be detected automatically by
a software tool which assists in drawing these diagrams.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 486 206]{./repeated.eps}
% repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 486 206
\label{fig:repeated}
\includegraphics[bb=0 0 485 206]{logic_diagram/repeated.jpg}
% repeated.jpg: 539x229 pixel, 80dpi, 17.11x7.27 cm, bb=0 0 485 206
\label{fig:repeat}
\end{figure}
% \begin{figure}[h]
% \centering
% \includegraphics[bb=0 0 486 206]{./repeated.jpg}
% % repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 486 206
% \label{fig:repeated}
% \end{figure}
The diagram \ref{fig:repeat} is converted to Boolean logic by first looking at the test cases, and
@ -515,13 +539,19 @@ Very often a failure mode can only occurr
given a searate environmental condition.
In Fault Tree Analysis (FTA) this is represented by an inhibit gate.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 364 228]{./inhibit.eps}
% inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
\includegraphics[bb=0 0 364 227]{logic_diagram/inhibit.jpg}
% inhibit.jpg: 404x252 pixel, 80dpi, 12.83x8.00 cm, bb=0 0 364 227
\label{fig:inhibit}
\end{figure}
%
% \begin{figure}[h]
% \centering
% \includegraphics[bb=0 0 364 228]{./inhibit.jpg}
% % inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
% \label{fig:inhibit}
% \end{figure}
The diagram \ref{fig:inhibit} has a test case in the contour $C$.
Contour $C$ is enclosed by contour $A$. This says
@ -540,7 +570,7 @@ represented, for the sake of this example, by contour $D$.
In terms of propositional logic, the inhibit gate of FTA, and the countour enclosure
of PLD represent {\em implication}.
\\
\tiny
% \tiny
\vspace{0.3cm}
\begin{tabular}{||c|c|c|c||} \hline \hline
{\em $c$ } & {\em $a$ } & {\em $R1$ } \\ \hline
@ -550,7 +580,7 @@ of PLD represent {\em implication}.
T & T & T \\ \hline \hline
\end{tabular}
\vspace{0.3cm}
\normalsize
% \normalsize
$$ R1 = c \implies a $$
$$ R2 = a $$

139
logic_diagram/logic_diagram.tex.backup
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@ -1,7 +1,4 @@
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.15 2009/02/09 07:33:27 robin Exp $
\end{verbatim}
\begin{abstract}
%This chapter describes using diagrams to represent propositional logic.
@ -37,6 +34,12 @@ for the analysis of safety critical software and hardware systems.
%\end{keyword}
%\end{frontmatter}
% In software looking at one condition means lots of dont care situations
% in static analysis we look at given sub-sets of faults and assume the other faults
% are not active.
% This is a major cultural difference !
% it deserves a whole chapter.
\section{Introduction}
@ -49,7 +52,7 @@ states. PLD provides a visual method for modelling failure~mode analysis
within these systems, and specifically
identifying common failure symptoms in a user friendly way.
Contrasting this to looking at many propositional logic equations directly
in a text editor or spreadsheet, a visual method is prefferred.
in a text editor or spreadsheet, a visual method is percieved as being more intuitive.
%Traditional set theory is often represented by Euler\cite{euler} or Spider\cite{spider}
@ -67,7 +70,8 @@ in a text editor or spreadsheet, a visual method is prefferred.
%these points may be joined.
PLDs use three visual features that
can be combined to represent logic equations. Closed contours (using dashed lines), test cases, and joining lines.
can be combined to represent logic equations. Closed contours, test cases, and lines that
link test cases.
All features may be labelled, and the labels must be unique within a diagram, however contours may be repeated in the diagram.
%Aditionally a label begining with the `$\neg$' character, applied only to a contour, represents negation.
@ -75,10 +79,11 @@ All features may be labelled, and the labels must be unique within a diagram, ho
%Regions defined by contours are used to represent given conjunctive logical conditions.
Test cases are marked by asterisks. These are used as a visual `anchor'
to mark a logical condition, the logical condition being defined by the countours
that enclose the region on which the test case has been placed.
Test cases may be pair-wise connected by named lines representing disjunction (Boolean `OR') of
the conditions defined by the placement of the test case markers.
to mark a logical condition, the logical condition being defined by the contours
that enclose the region on which the test~case has been placed.
The contours that enclose represent conjuction.
Test~cases may be connected by joining lines. These lines represent disjunction (Boolean `OR') of
test~cases.
With these three visual syntax elements, we have the basic building blocks for all logic equations possible.
\begin{description}
@ -372,7 +377,7 @@ Joining lines thus represent dis-junction in a PLD.
\begin{figure}[h+]
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldand.eps}
\includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldand.jpg}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
@ -419,6 +424,34 @@ substituting the test cases for their Boolean logic equations gives
$$ R = ((a) \vee (b)) $$.
\clearpage
\subsection {Labels and useage}
In diagram \ref{fig:ld_meq} Z and W were labeled but were not necessary for the final expression
of $ R = b \vee c $. The intended use of these diagrams, is that resultant logical conditions be used in a later stage of reasoning.
Test cases joined by disjunction, all become represented in one, resultant equation.
Therefore only test cases not linked by any disjunctive joining lines need be named.
The diagram \ref{fig:ld_meq} can therefore be represented as in diagram \ref{fig:ld_meq2}, with
two unnamed test cases.
\begin{figure}[h+]
%\centering
%\input{millivolt_sensor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{logic_diagram/ldmeq2.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.4]{ldmeq2.eps}
\caption{Several Logical Expressions with unamed test cases}
\label{fig:ld_meq2}
\end{figure}
\paragraph{How this would be interpreted in failure analysis}
In failure analysis, this could be considered to be a sub-system with two failure states $a$ and $b$.
The proposition $P$ considers the scenario where either failure~mode is active.
@ -437,31 +470,30 @@ of $a$ and $b$ both being active is not defined on this diagram.
Repeated contours are allowed in PLD diagrams.
Logical contradictions or tautologies can be detected automatically by
a software tool which assists in drawing these diagrams.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 640 480]{./repeated.jpg}
% repeated.jpg: 640x480 pixel, 72dpi, 22.58x16.93 cm, bb=0 0 640 480
\caption{Repeated Contours}
\label{fig:repeat}
\includegraphics[bb=0 0 486 206]{./repeated.eps}
% repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 486 206
\label{fig:repeated}
\end{figure}
The diagram \ref{fig:repeat} is converted to Boolean logic by first looking at the test cases, and
the contours they are placed on.
$$ P = (a) $$
$$ Q = (b) \wedge (c) $$
$$ P = (b) $$
$$ Q = (a) \wedge (c) $$
The two test cases are joined by a the line named $R1$.
we thus apply disjunction to the test cases.
$$ R1 = P \vee Q $$
$$ R1 = b \wedge ( a \vee c ) $$.
$$ R1 = b \vee ( a \wedge c ) $$.
$R2$ joins two other test cases
$$R2 = a \vee c $$
The test~case residing in the intersection of countours $B$ and $A$
represents the logic equation $R = a \wedge b$.
represents the logic equation $R3 = a \wedge b$.
\paragraph{How this would be interpreted in failure analysis}
In failure analysis, $R2$ is the symptom of either failure~mode $A$ or $C$
@ -479,35 +511,54 @@ There is an additional symptom, that of the test case in $A \wedge B$.
Very often a failure mode can only occurr
given a searate environmental condition.
In Fault Tree Analysis (FTA) this is represented by an inhibit gate.
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 640 480]{./inhibit.jpg}
% repeated.jpg: 640x480 pixel, 72dpi, 22.58x16.93 cm, bb=0 0 640 480
\caption{Inhibit Contours}
\includegraphics[bb=0 0 364 228]{./inhibit.eps}
% inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
\label{fig:inhibit}
\end{figure}
The diagram \ref{fig:inhibit} has a test case in the contour $C$.
Contour $C$ is enclosed by contour $A$. This says
that for failure~mode $C$ to occur failure mode $A$
must have occurred.
A well known example of this is the space shuttle `O' ring failure that
caused the 1986 challenger disaster \cite {wdycwopt}.
caused the 1986 challenger disaster \cite{wdycwopt}.
For the failure mode to occurr the ambiant temperature had to
be below a critical value.
If we take the failure mode of the `O' ring to be $C$
and the temperature below critical to be $A$, we can see that
the low temperature failure~mode $C$ can only occurr if $A$ is true.
The `O' ring could fail in a different way above the critical temperature and this is
represented, for the sake of this example, by contour $D$
The `O' ring could fail in a different way independant of the critical temperature and this is
represented, for the sake of this example, by contour $D$.
In terms of propositional logic, the inhibit gate of FTA, and the countour enclosure
of PLD represent {\em implication}.
\\
\tiny
\vspace{0.3cm}
\begin{tabular}{||c|c|c|c||} \hline \hline
{\em $c$ } & {\em $a$ } & {\em $R1$ } \\ \hline
F & F & T \\ \hline
F & T & T \\ \hline
T & F & F \\ \hline
T & T & T \\ \hline \hline
\end{tabular}
\vspace{0.3cm}
\normalsize
$$ R1 = c \implies a $$
$$ R2 = a $$
$$ R3 = d $$
\paragraph{How this would be interpreted in failure analysis}
In failure analysis, $R2$ is the symptom of either failure~mode $A$ or $C$
occurring. $R1$ is the symptom of $B$ or $A \wedge C$ occurring.
There is an additional symptom, that of the test case in $A \wedge B$.
Note that although R2 is a symptom of the sub-system, on its own
it will not lead to a dangerous failure~mode of the subsystem.
% \subsection { Representing Logical Negation }
@ -656,34 +707,6 @@ There is an additional symptom, that of the test case in $A \wedge B$.
% %\bibliography{vmgbibliography}
% %\normalsize
%
\clearpage
\subsection {Labels and useage}
In diagram \ref{fig:ld_meq} Z and W were labeled but were not necessary for the final expression
of $ R = b \vee c $. The intended use of these diagrams, is that resultant logical conditions be used in a later stage of reasoning.
Test cases joined by disjunction, all become represented in one, resultant equation.
Therefore only test cases not linked by any disjunctive joining lines need be named.
The diagram \ref{fig:ld_meq} can therefore be represented as in diagram \ref{fig:ld_meq2}, with
two unnamed test cases.
\begin{figure}[h+]
%\centering
%\input{millivolt_sensor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{logic_diagram/ldmeq2.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.4]{ldmeq2.eps}
\caption{Several Logical Expressions with unamed test cases}
\label{fig:ld_meq2}
\end{figure}
\section{Intended use in FMMD}
The intention for these diagrams is that they are used to collect
@ -712,7 +735,7 @@ must be less than or equal to the sum of the number of component faults.
%Typeset in \ \ {\huge \LaTeX} \ \ on \ \ \today
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.15 2009/02/09 07:33:27 robin Exp $
CVS Revision Identity $Id: logic_diagram.tex,v 1.17 2010/01/06 13:41:32 robin Exp $
\end{verbatim}
Compiled last \today
%\end{document}

145
logic_diagram/logic_diagram.tex~
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@ -1,7 +1,4 @@
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.15 2009/02/09 07:33:27 robin Exp $
\end{verbatim}
\begin{abstract}
%This chapter describes using diagrams to represent propositional logic.
@ -37,6 +34,12 @@ for the analysis of safety critical software and hardware systems.
%\end{keyword}
%\end{frontmatter}
% In software looking at one condition means lots of dont care situations
% in static analysis we look at given sub-sets of faults and assume the other faults
% are not active.
% This is a major cultural difference !
% it deserves a whole chapter.
\section{Introduction}
@ -49,7 +52,7 @@ states. PLD provides a visual method for modelling failure~mode analysis
within these systems, and specifically
identifying common failure symptoms in a user friendly way.
Contrasting this to looking at many propositional logic equations directly
in a text editor or spreadsheet, a visual method is prefferred.
in a text editor or spreadsheet, a visual method is percieved as being more intuitive.
%Traditional set theory is often represented by Euler\cite{euler} or Spider\cite{spider}
@ -67,7 +70,8 @@ in a text editor or spreadsheet, a visual method is prefferred.
%these points may be joined.
PLDs use three visual features that
can be combined to represent logic equations. Closed contours (using dashed lines), test cases, and joining lines.
can be combined to represent logic equations. Closed contours, test cases, and lines that
link test cases.
All features may be labelled, and the labels must be unique within a diagram, however contours may be repeated in the diagram.
%Aditionally a label begining with the `$\neg$' character, applied only to a contour, represents negation.
@ -75,10 +79,11 @@ All features may be labelled, and the labels must be unique within a diagram, ho
%Regions defined by contours are used to represent given conjunctive logical conditions.
Test cases are marked by asterisks. These are used as a visual `anchor'
to mark a logical condition, the logical condition being defined by the countours
that enclose the region on which the test case has been placed.
Test cases may be pair-wise connected by named lines representing disjunction (Boolean `OR') of
the conditions defined by the placement of the test case markers.
to mark a logical condition, the logical condition being defined by the contours
that enclose the region on which the test~case has been placed.
The contours that enclose represent conjuction.
Test~cases may be connected by joining lines. These lines represent disjunction (Boolean `OR') of
test~cases.
With these three visual syntax elements, we have the basic building blocks for all logic equations possible.
\begin{description}
@ -369,18 +374,24 @@ Joining lines thus represent dis-junction in a PLD.
\subsection{ Logical AND example }
\begin{figure}[h+]
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldand.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.6]{ldand.eps}
\caption{Logical AND}
\label{fig:ld_and}
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 279 247]{logic_diagram/ldand.jpg}
% ldand.jpg: 279x247 pixel, 72dpi, 9.84x8.71 cm, bb=0 0 279 247
\label{fig:ld_and}
\end{figure}
% \begin{figure}[h+]
% \begin{center}
% \includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldand.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
%
% %\includegraphics[scale=0.6]{ldand.eps}
% \caption{Logical AND}
% \label{fig:ld_and}
% \end{figure}
In the diagram \ref{fig:ld_and} the area of intersection between the contours $a$ and $b$
represents the conjunction of those conditions. The point $P$ represents the logic equation
@ -393,18 +404,24 @@ The proposition $P$ considers the scenario where both failure~modes are active.
\clearpage
\subsection { Logical OR example }
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 476 264]{logic_diagram/ldor.jpg}
% ldor.jpg: 476x264 pixel, 72dpi, 16.79x9.31 cm, bb=0 0 476 264
\label{fig:ld_or}
\end{figure}
\begin{figure}[h+]
%\centering
%\input{ldor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldor.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.60]{ldor.eps}
\caption{Logical OR}
\label{fig:ld_or}
\end{figure} % OR
% \begin{figure}[h+]
% %\centering
% %\input{ldor.tex}
% \begin{center}
% \includegraphics[width=200pt,bb=0 0 450 404]{logic_diagram/ldor.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
% %\includegraphics[scale=0.60]{ldor.eps}
% \caption{Logical OR}
% \label{fig:ld_or}
% \end{figure} % OR
The diagram \ref{fig:ld_or} is converted to Boolean logic by first looking at the test cases, and
@ -431,21 +448,26 @@ Therefore only test cases not linked by any disjunctive joining lines need be na
The diagram \ref{fig:ld_meq} can therefore be represented as in diagram \ref{fig:ld_meq2}, with
two unnamed test cases.
\begin{figure}[h+]
%\centering
%\input{millivolt_sensor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{logic_diagram/ldmeq2.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.4]{ldmeq2.eps}
\caption{Several Logical Expressions with unamed test cases}
\label{fig:ld_meq2}
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 572 297,scale=0.7,keepaspectratio=true]{./ldmeq2.jpg}
% ldmeq2.jpg: 572x297 pixel, 72dpi, 20.18x10.48 cm, bb=0 0 572 297
\label{fig:ld_meq2}
\end{figure}
%
% \begin{figure}[h+]
% %\centering
% %\input{millivolt_sensor.tex}
% \begin{center}
% \includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{logic_diagram/ldmeq2.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
% %\includegraphics[scale=0.4]{ldmeq2.eps}
% \caption{Several Logical Expressions with unamed test cases}
% \label{fig:ld_meq2}
% \end{figure}
\paragraph{How this would be interpreted in failure analysis}
In failure analysis, this could be considered to be a sub-system with two failure states $a$ and $b$.
@ -465,14 +487,23 @@ of $a$ and $b$ both being active is not defined on this diagram.
Repeated contours are allowed in PLD diagrams.
Logical contradictions or tautologies can be detected automatically by
a software tool which assists in drawing these diagrams.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 550 250]{./repeated.eps}
% repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 550 250
\includegraphics[bb=0 0 485 206]{logic_diagram/repeated.jpg}
% repeated.jpg: 539x229 pixel, 80dpi, 17.11x7.27 cm, bb=0 0 485 206
\label{fig:repeat}
\end{figure}
% \begin{figure}[h]
% \centering
% \includegraphics[bb=0 0 486 206]{./repeated.jpg}
% % repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 486 206
% \label{fig:repeated}
% \end{figure}
The diagram \ref{fig:repeat} is converted to Boolean logic by first looking at the test cases, and
@ -508,13 +539,19 @@ Very often a failure mode can only occurr
given a searate environmental condition.
In Fault Tree Analysis (FTA) this is represented by an inhibit gate.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 364 228]{./inhibit.eps}
% inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
\includegraphics[bb=0 0 364 227]{logic_diagram/inhibit.jpg}
% inhibit.jpg: 404x252 pixel, 80dpi, 12.83x8.00 cm, bb=0 0 364 227
\label{fig:inhibit}
\end{figure}
%
% \begin{figure}[h]
% \centering
% \includegraphics[bb=0 0 364 228]{./inhibit.jpg}
% % inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
% \label{fig:inhibit}
% \end{figure}
The diagram \ref{fig:inhibit} has a test case in the contour $C$.
Contour $C$ is enclosed by contour $A$. This says
@ -533,7 +570,7 @@ represented, for the sake of this example, by contour $D$.
In terms of propositional logic, the inhibit gate of FTA, and the countour enclosure
of PLD represent {\em implication}.
\\
\tiny
% \tiny
\vspace{0.3cm}
\begin{tabular}{||c|c|c|c||} \hline \hline
{\em $c$ } & {\em $a$ } & {\em $R1$ } \\ \hline
@ -543,7 +580,7 @@ of PLD represent {\em implication}.
T & T & T \\ \hline \hline
\end{tabular}
\vspace{0.3cm}
\normalsize
% \normalsize
$$ R1 = c \implies a $$
$$ R2 = a $$
@ -731,7 +768,7 @@ must be less than or equal to the sum of the number of component faults.
%Typeset in \ \ {\huge \LaTeX} \ \ on \ \ \today
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.15 2009/02/09 07:33:27 robin Exp $
CVS Revision Identity $Id: logic_diagram.tex,v 1.17 2010/01/06 13:41:32 robin Exp $
\end{verbatim}
Compiled last \today
%\end{document}

136
logic_diagram/logic_diagram_paper.tex
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@ -1,7 +1,4 @@
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.16 2010/01/01 14:09:02 robin Exp $
\end{verbatim}
\begin{abstract}
%This chapter describes using diagrams to represent propositional logic.
@ -37,6 +34,12 @@ for the analysis of safety critical software and hardware systems.
%\end{keyword}
%\end{frontmatter}
% In software looking at one condition means lots of dont care situations
% in static analysis we look at given sub-sets of faults and assume the other faults
% are not active.
% This is a major cultural difference !
% it deserves a whole chapter.
\section{Introduction}
@ -67,10 +70,10 @@ in a text editor or spreadsheet, a visual method is percieved as being more intu
%these points may be joined.
PLDs use three visual features that
can be combined to represent logic equations. Closed contours (using dashed lines), test cases, and lines that
can be combined to represent logic equations. Closed contours, test cases, and lines that
link test cases.
All features may be labelled, and the labels must be unique within a diagram, however contours may be repeated in the diagram.
Aditionally a label begining with the `$\neg$' character, applied only to a contour, represents negation.
%Aditionally a label begining with the `$\neg$' character, applied only to a contour, represents negation.
%Regions defined by contours are used to represent given conjunctive logical conditions.
@ -371,18 +374,24 @@ Joining lines thus represent dis-junction in a PLD.
\subsection{ Logical AND example }
\begin{figure}[h+]
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{ldand.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.6]{ldand.eps}
\caption{Logical AND}
\label{fig:ld_and}
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 279 247]{ldand.jpg}
% ldand.jpg: 279x247 pixel, 72dpi, 9.84x8.71 cm, bb=0 0 279 247
\label{fig:ld_and}
\end{figure}
% \begin{figure}[h+]
% \begin{center}
% \includegraphics[width=200pt,bb=0 0 450 404]{ldand.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
%
% %\includegraphics[scale=0.6]{ldand.eps}
% \caption{Logical AND}
% \label{fig:ld_and}
% \end{figure}
In the diagram \ref{fig:ld_and} the area of intersection between the contours $a$ and $b$
represents the conjunction of those conditions. The point $P$ represents the logic equation
@ -395,18 +404,24 @@ The proposition $P$ considers the scenario where both failure~modes are active.
\clearpage
\subsection { Logical OR example }
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 476 264]{ldor.jpg}
% ldor.jpg: 476x264 pixel, 72dpi, 16.79x9.31 cm, bb=0 0 476 264
\label{fig:ld_or}
\end{figure}
\begin{figure}[h+]
%\centering
%\input{ldor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0 0 450 404]{ldor.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.60]{ldor.eps}
\caption{Logical OR}
\label{fig:ld_or}
\end{figure} % OR
% \begin{figure}[h+]
% %\centering
% %\input{ldor.tex}
% \begin{center}
% \includegraphics[width=200pt,bb=0 0 450 404]{ldor.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
% %\includegraphics[scale=0.60]{ldor.eps}
% \caption{Logical OR}
% \label{fig:ld_or}
% \end{figure} % OR
The diagram \ref{fig:ld_or} is converted to Boolean logic by first looking at the test cases, and
@ -433,21 +448,26 @@ Therefore only test cases not linked by any disjunctive joining lines need be na
The diagram \ref{fig:ld_meq} can therefore be represented as in diagram \ref{fig:ld_meq2}, with
two unnamed test cases.
\begin{figure}[h+]
%\centering
%\input{millivolt_sensor.tex}
\begin{center}
\includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{ldmeq2.eps}
% resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
\end{center}
%\includegraphics[scale=0.4]{ldmeq2.eps}
\caption{Several Logical Expressions with unamed test cases}
\label{fig:ld_meq2}
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 572 297,scale=0.7,keepaspectratio=true]{ldmeq2.jpg}
% ldmeq2.jpg: 572x297 pixel, 72dpi, 20.18x10.48 cm, bb=0 0 572 297
\label{fig:ld_meq2}
\end{figure}
%
% \begin{figure}[h+]
% %\centering
% %\input{millivolt_sensor.tex}
% \begin{center}
% \includegraphics[width=200pt,bb=0pt 0pt 600pt 600pt]{ldmeq2.jpg}
% % resistor_pld.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 450 404
% \end{center}
% %\includegraphics[scale=0.4]{ldmeq2.eps}
% \caption{Several Logical Expressions with unamed test cases}
% \label{fig:ld_meq2}
% \end{figure}
\paragraph{How this would be interpreted in failure analysis}
In failure analysis, this could be considered to be a sub-system with two failure states $a$ and $b$.
@ -467,13 +487,23 @@ of $a$ and $b$ both being active is not defined on this diagram.
Repeated contours are allowed in PLD diagrams.
Logical contradictions or tautologies can be detected automatically by
a software tool which assists in drawing these diagrams.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 486 206]{./repeated.eps}
% repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 486 206
\label{fig:repeated}
\includegraphics[bb=0 0 485 206]{repeated.jpg}
% repeated.jpg: 539x229 pixel, 80dpi, 17.11x7.27 cm, bb=0 0 485 206
\label{fig:repeat}
\end{figure}
% \begin{figure}[h]
% \centering
% \includegraphics[bb=0 0 486 206]{./repeated.jpg}
% % repeated.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 486 206
% \label{fig:repeated}
% \end{figure}
The diagram \ref{fig:repeat} is converted to Boolean logic by first looking at the test cases, and
@ -509,13 +539,19 @@ Very often a failure mode can only occurr
given a searate environmental condition.
In Fault Tree Analysis (FTA) this is represented by an inhibit gate.
\begin{figure}[h]
\begin{figure}[h]
\centering
\includegraphics[bb=0 0 364 228]{./inhibit.eps}
% inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
\includegraphics[bb=0 0 364 227]{inhibit.jpg}
% inhibit.jpg: 404x252 pixel, 80dpi, 12.83x8.00 cm, bb=0 0 364 227
\label{fig:inhibit}
\end{figure}
%
% \begin{figure}[h]
% \centering
% \includegraphics[bb=0 0 364 228]{./inhibit.jpg}
% % inhibit.eps: 0x0 pixel, 300dpi, 0.00x0.00 cm, bb=0 0 364 228
% \label{fig:inhibit}
% \end{figure}
The diagram \ref{fig:inhibit} has a test case in the contour $C$.
Contour $C$ is enclosed by contour $A$. This says
@ -534,7 +570,7 @@ represented, for the sake of this example, by contour $D$.
In terms of propositional logic, the inhibit gate of FTA, and the countour enclosure
of PLD represent {\em implication}.
\\
\tiny
% \tiny
\vspace{0.3cm}
\begin{tabular}{||c|c|c|c||} \hline \hline
{\em $c$ } & {\em $a$ } & {\em $R1$ } \\ \hline
@ -544,7 +580,7 @@ of PLD represent {\em implication}.
T & T & T \\ \hline \hline
\end{tabular}
\vspace{0.3cm}
\normalsize
% \normalsize
$$ R1 = c \implies a $$
$$ R2 = a $$
@ -732,7 +768,7 @@ must be less than or equal to the sum of the number of component faults.
%Typeset in \ \ {\huge \LaTeX} \ \ on \ \ \today
\begin{verbatim}
CVS Revision Identity $Id: logic_diagram.tex,v 1.16 2010/01/01 14:09:02 robin Exp $
CVS Revision Identity $Id: logic_diagram.tex,v 1.17 2010/01/06 13:41:32 robin Exp $
\end{verbatim}
Compiled last \today
%\end{document}

19
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@ -4,32 +4,29 @@
\citation{FMEA}
\citation{SIL}
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