From 5fe54eddd3a3ed1912682c530bc0d590f7f1e11e Mon Sep 17 00:00:00 2001 From: Robin Clark Date: Fri, 13 Aug 2010 19:33:08 +0100 Subject: [PATCH] Refernces in the PLD --- .gitignore | 3 +++ logic_diagram/Makefile | 4 ++++ logic_diagram/logic_diagram.tex | 38 +++++++++++++++++++++------------ 3 files changed, 31 insertions(+), 14 deletions(-) diff --git a/.gitignore b/.gitignore index 8dd175e..263dbb5 100644 --- a/.gitignore +++ b/.gitignore @@ -13,3 +13,6 @@ *.toc *.*~ +*paper.tex +*.txt + diff --git a/logic_diagram/Makefile b/logic_diagram/Makefile index bb6f264..8d29472 100644 --- a/logic_diagram/Makefile +++ b/logic_diagram/Makefile @@ -16,3 +16,7 @@ paper: paper.tex logic_diagram_paper.tex # logic_diagram_paper.tex: logic_diagram.tex cat logic_diagram.tex | sed 's/logic_diagram\///' > logic_diagram_paper.tex + + +bib: logic_diagram_paper.tex + bibtex paper diff --git a/logic_diagram/logic_diagram.tex b/logic_diagram/logic_diagram.tex index 34e236d..62130c0 100644 --- a/logic_diagram/logic_diagram.tex +++ b/logic_diagram/logic_diagram.tex @@ -7,7 +7,7 @@ Propositial Logic Diagrams (PLD) have been designed to provide an intuitive meth a specific sub-set of logic equations, to express fault modes in Mechanical and Electronic Systems. PLDs are a variant of constraint diagrams. Contours used to express sets represent failure modes and the Symptomatically merged groups -are akin to the `spiders' of constraint diagrams\ref{constraint}. +are akin to the `spiders'\cite{howse:rwsd} of constraint diagrams\cite{gil:tafocd}. %To aid hierarchical stages of fault analysis, it has been specifically developed for the purpose of %joining conjunctive conditions with disjuctive conditions %to group the effects of failure modes. @@ -19,7 +19,7 @@ Nearly all modern safety critical systems involve these three disiplines. % It is intended to be used for analysis of automated safety critical systems. Many types of safety critical systems now legally -require fault mode effects analysis\cite{FMEA}, +require fault mode effects analysis\cite{sccs}[pp 38-39], but few formal systems exist and wide-spread take-up is not yet the norm.\cite{takeup}. % @@ -39,7 +39,7 @@ Propositial Logic Diagrams (PLD) have been designed to provide an intuitive meth a specific sub-set of logic equations, to express fault modes in Mechanical and Electronic Systems. PLDs are a variant of constraint diagrams. Contours used to express sets represent failure modes and the Symptomatically merged groups -are akin to the `spiders' of constraint diagrams\ref{constraint}. +are akin to the `spiders'\cite{howse:rwsd} of constraint diagrams\cite{gil:tafocd}. %To aid hierarchical stages of fault analysis, it has been specifically developed for the purpose of %joining conjunctive conditions with disjuctive conditions %to group the effects of failure modes. @@ -51,9 +51,9 @@ Nearly all modern safety critical systems involve these three disiplines. % It is intended to be used for analysis of automated safety critical systems. Many types of safety critical systems now legally -require fault mode effects analysis\cite{FMEA}, -but few formal systems exist and wide-spread take-up is -not yet the norm.\cite{takeup}. +require fault mode effects analysis\cite{sccs}[pp 38-39], +but few formal systems exist to assist in this, and wide-spread take-up is +not yet the norm.\cite{sccs}[pp 304-305]. % Because of its visual nature, it is easy to manipulate and model complicated conditions that can lead to dangerous failures in @@ -87,7 +87,7 @@ for the analysis of safety critical software and hardware systems. } Propositional Logic Diagrams (PLDs) have been created to collect and simplfy fault~modes in safety critical systems undergoing -static analysis\cite{FMEA}\cite{SIL}. +static analysis.%\cite{sccs}\cite{en61508}. % This type of analysis treats failure modes within a system as logical states. @@ -155,6 +155,8 @@ Definitions of concrete and abstract PLD's follow. Well-formedness conditions for PLD's are separated from this definition, because of practical differences between the way they are used to represent software as opposed to representing electronics and mechanical systems. +The concrete definitions for PLD's and Spider Diagrams\cite{howse:sd} share many common features. + \subsection{Concrete PLD Definition} @@ -362,7 +364,7 @@ $fmg$ in the diagram, where an SMG is a non empty set of test points $$ \mathcal{G}:SMG \rightarrow P_{fmg} $$ -The logic equation representing an SMG $p_{fmg}$ can be determined thus. +The logic equation (using $oplus$ to represent exclusive-or) representing an SMG $p_{fmg}$ can be determined thus. $$\mathcal{G}_{fmg}(fmg) = \bigoplus_{t \in fmg} (\; \mathcal{F}_{t} (t) \;) $$ } @@ -621,7 +623,7 @@ by the FMMD software tool. Very often a failure mode can only occur given a separate environmental condition. -In Fault Tree Analysis (FTA) this is represented by an inhibit gate.\cite{FTA}[pp41-42],\cite{NUK} +In Fault Tree Analysis (FTA) this is represented by an inhibit gate.\cite{nasafta}[pp41-42],\cite{nucfta} \begin{figure}[h] \centering @@ -641,17 +643,17 @@ The diagram \ref{fig:inhibit} has a test case in the contour $C$. Contour $C$ is \textbf{enclosed} by contour $A$. This says that for failure~mode $C$ to occur failure mode $A$ must have occurred. -A well known example of this is the space shuttle `O' ring failure that -caused the 1986 Challenger disaster \cite{wdycwopt}. +A famous example of this is the space shuttle `O' ring failure that +caused the 1986 Challenger disaster\cite{wdycwopt}. For the failure mode to occur, the ambient temperature had to be below a critical value. If we take the failure mode of the `O' ring to be $C$ and the temperature below critical to be $A$, we can see that the low temperature failure~mode $C$ can only occur if $A$ is true. -The `O' ring could fail in a different way independant of the critical temperature and this is +The `O' ring could fail in a different way independent of the critical temperature and this is represented, for the sake of this example, by contour $D$. -In terms of propositional logic, the inhibit gate of FTA, and the contour enclosure +In terms of propositional logic, the inhibit gate of FTAi\cite{nasafta}[pp 41-42], and the contour enclosure of PLD represent {\em implication}. \\ % \tiny @@ -777,7 +779,7 @@ it will not lead to a dangerous failure~mode of the subsystem. % F & F & T \\ \hline % F & T & T \\ \hline % T & F & F \\ \hline -% T & T & T \\ \hline \hline +% T & T & T \\ \hline \hline: % \end{tabular} % %\vspace{0.3cm} % \normalsize @@ -908,6 +910,14 @@ The test case AFE represents the condition where all four engines have failed. %\begin{verbatim} %CVS Revision Identity $Id: logic_diagram.tex,v 1.17 2010/01/06 13:41:32 robin Exp $ %\end{verbatim} +%\ifthenelse {\boolean{paper}} +%{ +% \bibliographystyle{plain} +% \bibliography{../vmgbibliography,../mybib} +% +%} +%{ +%} Compiled last \today %\end{document}