more polishing

mybib.bib

@@ -89,7 +89,7 @@ language={English}
 
 @INPROCEEDINGS{bayesfrequentist, 
 	author={Lyons, Loius.}, 
-	booktitle={Contenporary Physics: Bayes and Frequentism, A paticle physicists perspective},
+	booktitle={Contemporary Physics: Bayes and Frequentism, A paticle physicists perspective},
 	year={2013}, 
 	month={Feb}, 
 	volume={2}, 
@@ -388,8 +388,7 @@ ISSN={0149-144X},}
   YEAR =         "2008"
 }
 
-
+@incollection{theoremflower,
-@MISC{theoremflower,
 year={2004},
 isbn={978-3-540-21268-3},
 booktitle={Diagrammatic Representation and Inference},
@@ -404,6 +403,8 @@ author={Flower, Jean and Masthoff, Judith and Stapleton, Gem},
 pages={166-181}
 }
 
+
+
 % my bib file.
 @INPROCEEDINGS{automatingFMEA1281774,
 author={Papadopoulos, Y. and Parker, D. and Grante, C.},
@@ -464,7 +465,7 @@ year={2001},
 month={},
 volume={7},
 number={},
-pages={vol.7},
+pages={3458},
 keywords={Analytical models;Design automation;Design engineering;Discrete event simulation;Failure analysis;Hybrid power systems;Performance analysis;Production;Propulsion;Steady-state;aerospace computing;aerospace simulation;discrete event simulation;engineering computing;failure analysis;production engineering computing;CONFIG hybrid discrete event simulator;EPOCH Simulation for Failure Analysis software;EPOCH algorithm;automated incremental design FMEA;automatic generation;design models;engineering product/operations cross-cutting hybrid simulation ;failure modes;failure modes/effects analysis;functional labels;propellant production plant;scenario scripts;scenario-based analyses;space systems;timestep modeling;},
 doi={10.1109/AERO.2001.931423},
 ISSN={}}

submission_thesis/CH1_introduction/copy.tex

@@ -121,7 +121,7 @@ The primary motive for writing the Spider diagram editor was to provide an alter
 to formal languages for software specification.
 %
 An added attraction for using spider diagrams was that they could be used in 
-proving logic~\cite{stapleton:atpieds} and theorems~\cite{theoremflower,Fish200553} in an intuitive way.
+proving logic and theorems~\cite{theoremflower,Fish200553} in an intuitive way.
 %
 Because of the author's daily work exposure to FMEA, 
 %I started thinking 

submission_thesis/CH6_Software_Examples/software.tex

@@ -499,7 +499,8 @@ the failure modes for the new {\dc} are: %we state:
 $$fm ( CMATV ) =  \{ HIGH , LOW, V\_ERR \} .$$
 %
 %
-\paragraph{software and hardware hybrid {\fg} ---  RADC}
+\paragraph{Software and hardware hybrid {\fg} ---  RADC}
+\label{sec:readadc}
 \label{readADC}
 The software function \cf{Read\_ADC} uses the ADC hardware analysed
 as the {\dc} CMATV above.
@@ -522,8 +523,10 @@ The reference voltage for the ADC has a 0.1\% accuracy requirement.
 %
 If the reference value is outside this, it is also a {\fm}
 of this function, 
-which is termed $V\_REF$ (nb: this failure mode is detectable %observable
+which is termed $V\_REF$\footnote{The  failure mode $V\_REF$ is detectable %observable
-only if a test input is used to measure a high precision voltage reference).
+only if a test input is used to measure a high precision voltage reference.
+This validates the supply voltage to the ADC.
+This is common practise for safety critical readings when using an ADC.}.
 %
 Taken as a component for use in FMEA/FMMD the function has
 two failure modes. Therefore it can be treated as a generic component, $Read\_ADC$,
@@ -1019,9 +1022,9 @@ Identified Software Components:
 \begin{itemize}
  \item --- \cf{Monitor} (which calls PID algorithm and sets status LEDS),
  \item --- \cf{PID} (which calls \cf{determine\_set\_point\_error} and \cf{output\_control}),
- \item --- \cf{determine\_set\_point\_error} (which calls convert\_ADC\_to\_T),
+ \item --- \cf{determine\_set\_point\_error} (which calls \cf{convert\_ADC\_to\_T}),
- \item --- \cf{convert\_ADC\_to\_T} (which calls read\_ADC which we can re-use from the last example),
+ \item --- \cf{convert\_ADC\_to\_T} (which calls \cf{read\_ADC}), % which has been analysed as the {\dc} read\_ADC which can be re-used.} % from the last example),
- \item --- \cf{read\_ADC},
+ \item --- \cf{read\_ADC} (analysed in the previous section~\ref{sec:readadc}),
  \item --- \cf{output\_control} (which sets the PWM hardware according to the PID demand value).
 \end{itemize}
 %
@@ -1100,7 +1103,7 @@ Failure symptoms are collected and the {\dc} created with the following failure
 %
 %
 $$fm(Get\_Temperature) = \{  Pt100\_out\_of\_range, temp\_incorrect \} . $$
-\clearpage
+%\clearpage
 %
 %
 Following the afferent flow further, the function to determine the control error value is examined.

submission_thesis/CH7_Evaluation/copy.tex

@@ -28,8 +28,8 @@ The reasoning distances obtained from the FMMD examples (see chapter~\ref{sec:ch
 compared against {\XFMEA}.
 \fmmdglossXFMEA
 %
-Following on from the formal definitions, `unitary state failure modes' are defined. In short these
+Following on from formal definitions, `unitary state failure modes' are defined, i.e. 
-ensure that component failure modes are mutually exclusive. % Using the unitary state failure mode definition
+ensuring that component failure modes are mutually exclusive. % Using the unitary state failure mode definition
 %
 Standard formulae for combinations are then used to develop the concept of 
 the cardinality constrained power-set.
@@ -146,7 +146,7 @@ Using the language developed in the previous chapters,
 a system for analysis is considered as a collection %{\fg} 
 of components.
 %
-This is a set of components $G$, and the number of components in it  
+This set of components is termed $G$, and the number of components in it  by
 $ | G | $. %,
 %(an indexing and sub-scripting notation to identify particular {\fgs}
 %within an FMMD hierarchy is given in section~\ref{sec:indexsub}).
@@ -293,7 +293,7 @@ The comparison complexity function $CC$ is overloaded, to obtain the comparison
 \fmmdglossRD
 %\pagebreak[4]
 The  amplifier example from chapter~\ref{sec:chap4}, which has two
-stages, the potential divider and then the amplifier is chosen as an example for comparison complexity.
+stages, the potential divider and then the amplifier, is chosen as an example for comparison complexity.
 %
 The complexities are added from
 both these stages to determine how many reasoning paths there were to perform FMMD analysis on the 
@@ -557,9 +557,10 @@ are presented in the following table~\ref{tbl:firstcc}.
 %
 %\usepackage{multirow}
 \begin{table}
- \label{tbl:firstcc}
+% fucker \label{tbl:firstcc}
 
 \begin{tabular}{ |c|l|l|c| } 
+% ARRGGGGG\label{tbl:firstcc}
 \hline 
 \textbf{Hierarchy}   & \textbf{Derived}      & \textbf{Complexity} & $|fm(c)|$: \textbf{number}     \\
 \textbf{Level}       & \textbf{Component}    & \textbf{Comparison} & \textbf{of derived}                  \\
@@ -617,6 +618,7 @@ are presented in the following table~\ref{tbl:firstcc}.
 
 \end{tabular}
 \caption{Comparison Complexity figures for the first three examples in Chapter~\ref{sec:chap5}.}
+\label{tbl:firstcc} %%% LABELS ONLY WORK AFTER THE CAPTION IN LATEX
 \end{table}
  % end table
 The complexity comparison figures for the example circuits in chapter~\ref{sec:chap5} show 
@@ -637,11 +639,12 @@ It was also analysed twice, once by
 {na\"{\i}vely} using the first {\fgs} identified, and secondly by de-composing 
 the circuit further.
 %
-These two analyses are used to compare the effect on comparison complexity % REF DOES NOT WORK (see table~\ref{tbl:bubbacc11}) 
+These two analyses are used to compare the effect on comparison complexity % REF DOES NOT WORK 
+(see table~\ref{tbl:bubbacc11}) % put table labels after the caption.
 with that of {\XFMEA}.
 %
 \begin{table}
-\label{tbl:bubbacc11}
+
 % 
 \begin{tabular}{ |c|l|l|c| }
 
@@ -703,6 +706,7 @@ with that of {\XFMEA}.
 \end{tabular}
 %\label{tbl:bubbacc}
 \caption{Complexity Comparison figures for the Bubba Oscillator FMMD example (see section~\ref{sec:bubba}).}
+\label{tbl:bubbacc11}
 \end{table}
 %
 The initial {na\"{\i}ve} FMMD analysis reduces the number of checks by around a third, the more de-composed analysis
@@ -778,7 +782,7 @@ That is the signal path crosses from analogue to digital signalling and vice ver
 \label{sec:unitarystate}
 %\label{ch7:mutex}
 \label{ch7:mutex}
-\paragraph{Design Decision/Constraint}
+\paragraph{Design Decision/Constraint.}
 %
 An important factor in defining a set of failure modes is that they
 should represent the failure modes as simply and minimally as possible.
@@ -898,7 +902,7 @@ for base~components this is usually the case.
 Most simple components fail in one
 clearly defined way and generally stay in that state. 
 %
-Traditional FMEA has problems dealing with non unitary state failure modes.
+Traditional FMEA also has problems dealing with non unitary state failure modes.
 %
 This is mainly because combinations of failure modes could cause
 effects very difficult to predict (as they are in effect new failure modes of the component).
@@ -922,9 +926,9 @@ inside the micro-controller package.
 %
 The micro-controller thus becomes a collection of smaller components
 that can be analysed separately~\footnote{It is common for the signal paths
-in a safety critical product to be traced, and when entering a complex
+in a safety critical product to be traced,  when examining a complex
 component like a micro-controller, the process of heuristic de-compostion
-is then applied to it.}.
+is  typically applied.}.
 %
 %\paragraph{Reason for FMMD unitary failure mode constraint.} 
 Were this constraint not to be applied,

vmgbibliography.bib

@@ -20,12 +20,7 @@
 }
 
 
-@ARTICLE{stapleton:atpieds,
+
-  AUTHOR =       "G.~Stapleton and J.~Masthoff and J.~Flower and A.~Fish and J.~Southern",
-  TITLE =        "Automated Theorem Proving in {E}uler Diagrams Systems",
-  JOURNAL =      "Accepted for Journal of Automated Reasoning",
-  YEAR =         "to appear 2007"
-}
 
 @ARTICLE{stapleton:teacosdawc,
   AUTHOR =       "G. Stapleton and J. Taylor and J. Howse and S. Thompson",