diff --git a/submission_thesis/CH3_FMEA_criticism/copy.tex b/submission_thesis/CH3_FMEA_criticism/copy.tex index 1abffef..2d411cd 100644 --- a/submission_thesis/CH3_FMEA_criticism/copy.tex +++ b/submission_thesis/CH3_FMEA_criticism/copy.tex @@ -1,4 +1,6 @@ -\section{Origin of FMEA} +\section{Historical Origins of FMEA} +\subsection{FMEA designed for simple electro-mechanical systems} + \section{Reasoning Distance} \section{Comparison Complexity} diff --git a/submission_thesis/CH5_Examples/circuit1001.png b/submission_thesis/CH5_Examples/circuit1001.png index 7652287..ce142e3 100644 Binary files a/submission_thesis/CH5_Examples/circuit1001.png and b/submission_thesis/CH5_Examples/circuit1001.png differ diff --git a/submission_thesis/CH5_Examples/circuit3003.png b/submission_thesis/CH5_Examples/circuit3003.png index 855ca00..17d4f2a 100644 Binary files a/submission_thesis/CH5_Examples/circuit3003.png and b/submission_thesis/CH5_Examples/circuit3003.png differ diff --git a/submission_thesis/CH5_Examples/copy.tex b/submission_thesis/CH5_Examples/copy.tex index fc58130..f3ae8b6 100644 --- a/submission_thesis/CH5_Examples/copy.tex +++ b/submission_thesis/CH5_Examples/copy.tex @@ -973,7 +973,7 @@ when it becomes a V2 follower). \end{figure} The {\fm} $DiffAMPIncorrect$ may seem like a vague {\fm}---however, this {\fm} is currently impossible to detect--- -in fault finding terminology~\cite{garrett}~\cite{mawokinski} this {\fm} is said to be unobservable, and in EN61508 +in fault finding terminology~\cite{garrett}~\cite{maikowski} this {\fm} is said to be unobservable, and in EN61508 terminology is called an undetectable fault. Were this failure to have safety implications this FMMD analysis will have revealed the un-observability and prompt re-design of this @@ -1669,6 +1669,9 @@ The following example shows the analysis of a mixed analogue and digital circuit +\nocite{f77} +\nocite{sccs} +\nocite{electronicssysapproach} \begin{figure}[h] \centering @@ -1698,6 +1701,105 @@ of the input voltage. The output of the flip flop, is now cleaned as an analogue signal (i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage) and fed into the summing integrator completing the negative feedback loop. + +\subsection{FMMD analysis of $\Sigma \Delta $ADC} + +The partslist for the $\Sigma \Delta $ADC + +$$\{ IC1, IC2, IC3 IC4 \} $$. + +IC1,2 and 3 are all Op-amps and we have failure modes from section~\ref{sec:opampfm}. + +$$ fm(OPAMP) = \{ HIGH, LOW, NOOP, LOW\_SLEW \} $$ + +We examine the literature for a failure model for the D-type flip flop~\cite{fmd91}[3-105], the CD4013B~\cite{cd4013Bds}, +and obtain its failure modes, which we can express using the $fm$ function: + +$$ fm ( CD4013B) = \{ HIGH, LOW, NOOP \} $$ + +The resistors and capacitor failure modes we take from EN298~\cite{en298}[An.A] + +$$ fm ( R ) = \{OPEN, SHORT\} $$ + + +$$ fm ( C) = \{OPEN, SHORT\} $$ + +We now need to choose {\fgs}. The signal path is circular, but we can start +with the input voltage, which is applied to $R2$, we can term this voltage $V_{in}$. +$R2$ and $R1$ form a summing junction to IC1. +$R1$ supplies the feedback voltage for the ADC, we can term this voltage as $V_{fb}$ +This can be our first {\fg}. For the symptoms, we have to think in terms of the effect +on its performance as a summing junction and not be +distracted by the integrator formed by $C_1$ and $IC1$. + +$$G^0_1 = \{R1, R2\}$$ + +\begin{table}[h+] +\caption{R1,R2 Summing Junction: Failure Mode Effects Analysis} % title of Table +\label{tbl:sumj} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + \textbf{Failure Scenario} & & \textbf{failure result} & & \textbf{Symptom} \\ + & & & & \\ + \hline\hline + FS1: $R1$ $OPEN$ & & $V_{in}$ dominates input & & $V_{in} DOM$ \\ + FS2: $R1$ $SHORT$ & & $V_{fb}$ dominates input & & $V_{fb} DOM$ \\ \hline + FS3: $R2$ $OPEN$ & & $V_{fb}$ dominates input & & $V_{fb} DOM$ \\ + FS4: $R2$ $SHORT$ & & $V_{in}$ dominates input & & $V_{in} DOM$ \\ \hline + +\hline + +\end{tabular} +\end{table} + + +From the analysis in table~\ref{tbl:sumj}, we can now create a derived component +$SUMJ$ which has the failure modes from collecting its symptoms. +We can state + +$$ fm(SUMJ) = \{ V_{in} DOM, V_{in} DOM \} $$ + + +Following along the signal path, the next functional group is the integrator. +This integrator is simply by $IC2$. This performs the function of +isolating the integrator from any load on its output. We can therefore include this as well. + +$$G^0_2 = \{IC1, C1, IC2\}$$ + + + +\begin{table}[h+] +\caption{IC1,C1,IC2 Buffered Integrator: Failure Mode Effects Analysis} % title of Table +\label{tbl:intg} + +\begin{tabular}{|| l | l | c | c | l ||} \hline + \textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ + & & & & \\ + \hline \hline + FS1: $IC1$ $HIGH$ & & output perm. high & & HIGH \\ + FS2: $IC1$ $LOW$ & & output perm. low & & LOW \\ \hline + FS3: $IC1$ $NOOP$ & & no current to drive C1 & & NO\_INTEGRATION \\ + FS4: $IC1$ $LOW\_SLEW$ & & signal delay to C1 & & NO\_INTEGRATION \\ \hline + + FS3: $C1$ $OPEN$ & & no capacitance & & NO\_INTEGRATION \\ + FS4: $C1$ $SHORT$ & & no capacitance & & NO\_INTEGRATION \\ \hline + +\hline + FS1: $IC2$ $HIGH$ & & output perm. high & & HIGH \\ + FS2: $IC2$ $LOW$ & & output perm. low & & LOW \\ \hline + FS3: $IC2$ $NOOP$ & & no current drive & & LOW \\ + FS4: $IC2$ $LOW\_SLEW$ & & delayed signal & & LOW\_SLEW \\ \hline +\hline + +\end{tabular} +\end{table} + + +From the analysis in table~\ref{tbl:intg}, we can now create a derived component +$SUMJ$ which has the failure modes from collecting its symptoms. +We can state + +$$ fm (SUMJ) = \{ HIGH, LOW, NO\_INTEGRATION , LOW\_SLEW \} $$ % ] % into % @@ -2044,8 +2146,9 @@ by separate wires and the resistance in those are effectively cancelled out by considering the voltage reading over $R_3$ to be relative. % The Pt100 element is a precision part and will be chosen for a specified accuracy/tolerance range. -One or other of the load resistors (the one we measure current over) should -be of a specified accuracy. +One or other of the load resistors (the one we measure current over) should also +be of a specified accuracy\footnote{It is common for standard surface mount resistors to have an +accuracy of $\pm 1\%$. Higher accuracy parts may be specified} % The \ohms{2k2} loading resistors should have a good temperature co-effecient (i.e. $\leq \; 50(ppm)\Delta R \propto \Delta \oc $). @@ -2843,7 +2946,7 @@ This voltage range forms our input requirement. We can now examine a software function that performs a conversion from the voltage read to a per~mil representation of the {\ft} input current. % -For the purpose of example the `C' programming language~\cite{kandr} is used. +For the purpose of example the `C' programming language~\cite{DBLP:books/ph/KernighanR88} is used. We initially assume a function \textbf{read\_ADC} which returns a floating point %double precision value which represents the voltage read (see code sample in figure~\ref{fig:code_read_4_20_input}). diff --git a/submission_thesis/mybib.bib b/submission_thesis/mybib.bib index 430fa1b..5319644 100644 --- a/submission_thesis/mybib.bib +++ b/submission_thesis/mybib.bib @@ -191,8 +191,29 @@ } +@book{electronicssysapproach, + added-at = {2011-03-24T00:00:00.000+0100}, + author = {Storey, Neil}, + biburl = {http://www.bibsonomy.org/bibtex/2b735c0730d88e197a34a649611f025c9/dblp}, + interhash = {db538f6c4e7c703ae5b1bda8764e626a}, + intrahash = {b735c0730d88e197a34a649611f025c9}, + isbn = {978-0-13-129396-0}, + keywords = {dblp}, + pages = {I-XII, 1-645}, + publisher = {Pearson / Prentice Hall}, + timestamp = {2011-03-24T00:00:00.000+0100}, + title = {Electronics - a systems approach (4. ed.).}, + year = 2009 +} +@PHDTHESIS{garrett, + AUTHOR = "Chris Garrett", + TITLE = "Functional diagnosis strategies for analog systems using heuristic programming techniques", + SCHOOL = "Brighton University, School of Electrical Engineering", + YEAR = "1989" +} + @PHDTHESIS{maikowski, AUTHOR = "Leo M Maikowski", TITLE = "Tolreranced Multiple Fault Diagnosis of Analog Circuits",