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Fixing refs plus JMC Proof read

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Robin Clark 2012-12-08 09:34:28 +00:00
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22
submission_thesis/CH5_Examples/copy.tex
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@ -45,7 +45,7 @@ is examined,
where re-use is appropriate in the first stage and where re-use is appropriate in the first stage and
not in the second. not in the second.
\item Section~\ref{sec:fivepolelp} analyses a Sallen-Key based five pole low pass filter. \item Section~\ref{sec:fivepolelp} analyses a Sallen-Key based five pole low pass filter.
It demonstrates re-use the first Sallen-Key analysis, %encountered as a {\dc} It demonstrates re-use of the first Sallen-Key analysis, %encountered as a {\dc}
increasing test efficiency. This example also serves to show a deep hierarchy of {\dcs}. increasing test efficiency. This example also serves to show a deep hierarchy of {\dcs}.
\item Section~\ref{sec:bubba} shows FMMD applied to a \item Section~\ref{sec:bubba} shows FMMD applied to a
loop topology---using a `Bubba' oscillator---demonstrating how FMMD differs from fault diagnosis techniques. loop topology---using a `Bubba' oscillator---demonstrating how FMMD differs from fault diagnosis techniques.
@ -943,8 +943,8 @@ For the unconstrained case, we have to consider all three components as one larg
The circuit in figure~\ref{fig:circuit1} amplifies the difference between The circuit in figure~\ref{fig:circuit1} amplifies the difference between
the input voltages $+V1$ and $+V2$. the input voltages $+V1$ and $+V2$.
The circuit is configured so that both inputs use the non-inverting, The circuit is configured so that both inputs use the non-inverting (high impedance inputs)
and thus high impedance inputs, meaning that they will not ensuring that they will not
electrically load the previous stage. electrically load the previous stage.
%over-load and/or unduly influence %over-load and/or unduly influence
%the sensors or circuitry supplying the voltage signals used for measurement. %the sensors or circuitry supplying the voltage signals used for measurement.
@ -1305,12 +1305,12 @@ However, from a failure mode perspective we can analyse it in a very similar way
to a potential divider (see section~\ref{subsec:potdiv}). to a potential divider (see section~\ref{subsec:potdiv}).
Capacitors generally fail OPEN but some types fail OPEN and SHORT. Capacitors generally fail OPEN but some types fail OPEN and SHORT.
We will consider the worst case two failure mode model for this analysis. We will consider the worst case two failure mode model for this analysis.
We analyse the first order low pass filter in table~\ref{tbl:firstorderlp}.\\ We analyse the first order low pass filter in table~\ref{tbl:firstorderlpass}.\\
\begin{table}[h+] \begin{table}[h+]
\caption{FirstOrderLP: Failure Mode Effects Analysis: Single Faults} % title of Table \caption{FirstOrderLP: Failure Mode Effects Analysis: Single Faults} % title of Table
\label{tbl:firstorderlp} \label{tbl:firstorderlpass}
\begin{tabular}{|| l | c | l ||} \hline \begin{tabular}{|| l | c | l ||} \hline
%\textbf{Failure Scenario} & & \textbf{First Order} & & \textbf{Symptom} \\ %\textbf{Failure Scenario} & & \textbf{First Order} & & \textbf{Symptom} \\
@ -1533,7 +1533,7 @@ We now can create a {\dc} to represent the circuit in figure~\ref{fig:circuit2},
$FivePoleLP$ and applying the $fm$ function to it (see table~\ref{tbl:fivepole}) yields $fm(FivePoleLP) = \{ HIGH, LOW, FilterIncorrect, NO\_SIGNAL \}$. $FivePoleLP$ and applying the $fm$ function to it (see table~\ref{tbl:fivepole}) yields $fm(FivePoleLP) = \{ HIGH, LOW, FilterIncorrect, NO\_SIGNAL \}$.
\pagebreak[4] %\pagebreak[4]
The failure modes for the low pass filters are very similar, and the propagation of the signal The failure modes for the low pass filters are very similar, and the propagation of the signal
is simple (as it is never inverted). The circuit under analysis is -- as shown in the block diagram (see figure~\ref{fig:blockdiagramcircuit2}) -- is simple (as it is never inverted). The circuit under analysis is -- as shown in the block diagram (see figure~\ref{fig:blockdiagramcircuit2}) --
@ -1546,6 +1546,8 @@ This example shows the analysis of a linear signal path circuit with three easil
{\fgs} and re-use of the Sallen-Key {\dc}. {\fgs} and re-use of the Sallen-Key {\dc}.
\clearpage \clearpage
\section{Quad Op-Amp Oscillator} \section{Quad Op-Amp Oscillator}
\label{sec:bubba} \label{sec:bubba}
@ -1830,7 +1832,7 @@ there are more {\dcs} and therefore increases the potential for re-use of pre-an
% HTR The more we can modularise, the more we decimate the $O(N^2)$ effect % HTR The more we can modularise, the more we decimate the $O(N^2)$ effect
% HTR of complexity comparison. % HTR of complexity comparison.
% %
\subsection{conclusion} \subsection{Conclusion}
With FMMD there is always a choice for the membership of {\fgs}. With FMMD there is always a choice for the membership of {\fgs}.
This example has shown that the simple approach, identifying This example has shown that the simple approach, identifying
initial {\fgs} and using them to build a large {\fg} to model the circuit initial {\fgs} and using them to build a large {\fg} to model the circuit
@ -1897,7 +1899,7 @@ and fed to the D type flip flop.
% %
% %
The output of the flip flop is routed to the digital output and to the feedback loop. The output of the flip flop is routed to the digital output and to the feedback loop.
It must be level converted before being fed to the analogue feedback. It must be level converted, i.e. from digital logic voltage levels to analogue levels, before being fed to the analogue feedback.
It is level converted to an analogue signal by IC3. It is level converted to an analogue signal by IC3.
(i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage) (i.e. a digital 0 becomes a -ve voltage and a digital 1 becomes a +ve voltage)
and fed into the summing integrator completing the negative feedback loop. and fed into the summing integrator completing the negative feedback loop.
@ -1954,7 +1956,7 @@ This can be our first {\fg} and we analyse it in table~\ref{tbl:sumjint}.
% %
$$FG = \{R1, R2, IC1, C1 \}$$ $$FG = \{R1, R2, IC1, C1 \}$$
That is the failure modes (see FMMD analysis at ~\ref{detal:SUMJINT})of our new {\dc} That is the failure modes (see FMMD analysis at~\ref{detail:SUMJINT})of our new {\dc}
$SUMJINT$ are $$\{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$ $SUMJINT$ are $$\{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \} .$$
\clearpage \clearpage
@ -2004,7 +2006,7 @@ We now form a {\fg} from $PD $ and $IC3$.
% %
$$ FG = \{ PD , IC3 \} $$ $$ FG = \{ PD , IC3 \} $$
% %
We now analyse this {\fg} (see section~\ref{detail:DS2AS}). We now analyse this {\fg} (see section~\ref{detail:DL2AL}).
$$ fm (DL2AL) = \{ LOW, HIGH, LOW\_{SLEW} \} $$ $$ fm (DL2AL) = \{ LOW, HIGH, LOW\_{SLEW} \} $$

2
submission_thesis/appendixes/detailed_analysis.tex
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@ -326,7 +326,7 @@ $SUMJINT$ we obtain $$\{ V_{in} DOM, V_{fb} DOM, NO\_INTEGRATION, HIGH, LOW \
\begin{table}[h+] \begin{table}[h+]
\center \center
\caption{$PD , IC3$ Digital level to analogue level converter: Failure Mode Effects Analysis} % title of Table \caption{$PD , IC3$ Digital level to analogue level converter: Failure Mode Effects Analysis} % title of Table
\label{tbl:DS2AS} \label{tbl:DL2AL}
\begin{tabular}{|| l | l | c | c | l ||} \hline \begin{tabular}{|| l | l | c | c | l ||} \hline
%\textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\ %\textbf{Failure Scenario} & & \textbf{failure result } & & \textbf{Symptom} \\